The semiconductor industry is at a critical juncture. Artificial intelligence is fueling unprecedented demand for computing performance, memory bandwidth, and system-level innovation, driving the industry toward what many leaders describe as a structural transformation, rather than a typical market cycle.

However, opportunities and challenges coexist, bringing with them a complex array of challenges—power constraints, supply chain pressures, rising costs, and technological complexity—that now extend far beyond traditional transistor size scaling.

At the recent SEMI Industry Strategy Symposium (ISS), Mark Fuselier, Senior Vice President of Technology and Product Engineering at AMD, and Naga Chandrasekaran, Executive Vice President and Chief Technology and Operations Officer of Intel's Foundry division, delivered keynote speeches, offering complementary perspectives on how the industry can evolve to meet the demands of the AI era. Their presentations revolved around several core themes: energy-efficient computing, system-level co-optimization, advanced packaging and interconnect innovation, supply chain resilience, and the necessity of ecosystem-wide collaboration.

Combined with recent technical work on energy-efficient AI architectures, it is clear that semiconductor innovation is shifting from device-centric scaling to holistic optimization of wafer fabrication processes, packaging, architecture, and system integration.

Driven by artificial intelligence

Both speakers emphasized that artificial intelligence is not just another wave of applications. On the contrary, it fundamentally reshapes the requirements for semiconductor technology.

Artificial intelligence as a structural driver of semiconductor growth

"We should all be very proud of what we've accomplished," Chandrasekaran said, reflecting on the industry's role in driving the rapid development of artificial intelligence. "But the foundation for all of this was laid decades ago." The scale of growth is unprecedented. AI workloads—especially large language models and generative AI systems—have placed exponentially increasing demands on computing power, memory bandwidth, and interconnect throughput. Training clusters now consist of thousands to tens of thousands of accelerators connected in vertically and horizontally scaled architectures, significantly increasing system-level power consumption and data transfer requirements.

This shift has fundamentally changed where innovation occurs. Computational scaling is no longer confined to the chip level but occurs at the cluster level, where network efficiency, thermal constraints, and power supply directly impact achievable performance.

Fuselier emphasized the severity of the challenge, noting that training cutting-edge models today may require sustained, massive-scale computations. "From a business perspective, this doesn't work," he stressed, emphasizing that brute-force scaling must be replaced by efficiency improvements.

Energy efficiency

Historically, advancements in semiconductor technology have been primarily measured by increases in frequency and transistor density. In the age of artificial intelligence, performance per watt has become the main metric.

Energy efficiency became the primary design constraint.

Energy-efficient AI architectures now need to reduce energy consumption per operation while increasing overall compute throughput. According to recent technical findings published by Fuselier and AMD engineers, improving accelerator efficiency directly improves data center-level efficiency because it reduces the number of nodes required to achieve a given performance target, thereby reducing network overhead and cooling requirements.

This shift reflects a fundamental change in architecture. AI workloads are primarily driven by parallel computation and data transfer, rather than serial execution. Therefore, shortening the distance between compute and memory has become one of the most effective means of reducing energy consumption.

Shortening the data path reduces latency and energy consumption per bit, making heterogeneous integration and memory proximity crucial design strategies. Advanced packaging technologies, such as 3D stacking, allow for tighter integration of compute and memory, significantly reducing data transfer energy consumption.

Fuselier describes this evolution as a paradigm shift: delivering compute power at lower voltages rather than maximizing frequency. Lower operating voltages reduce dynamic power consumption, especially important in high-utilization AI data center environments where dynamic power consumption dominates total energy consumption.

The Co-optimization

Energy-efficient AI architectures are increasingly relying on chipset-based approaches rather than monolithic designs. Modular chipsets allow each functional module (compute, memory, I/O) to be manufactured using the most suitable process node, thereby improving performance and energy efficiency.

Chiplet, 3D integration, and architectural co-optimization

Recent accelerator designs embody this shift. For example, AMD's MI300 architecture integrates multiple accelerator complex chips (XCDs) and input/output chips (IODs) using 2.5D interposer technology, while employing 3D stacking techniques to increase compute density and reduce power consumption. Integrating large in-package caches (such as Infinity Cache) reduces DRAM accesses and lowers average memory access power consumption by shortening the path between memory and compute engines.

This architectural approach reflects a broader industry trend. Improving compute density and efficiency at the scale of artificial intelligence can no longer be achieved simply by shrinking transistor size. Instead, co-optimization of design techniques—combining architectural choices with packaging and process technologies—has become crucial (Figure 1).

This means that system architecture decisions now have just as much impact on energy efficiency as process node selection.

Energy-saving computing technology

Despite increasing focus on packaging and architecture, process technology remains a key factor in improving energy efficiency.

Energy-efficient computing (EEC) optimization primarily focuses on three areas: dynamic and static power consumption optimization, reduction of parasitic effects in transistor and interconnect structures, and improvement of inherent device electrostatic performance.

Lowering the supply voltage (Vdd) is one of the most effective means of reducing dynamic power consumption, but it comes with trade-offs in leakage power consumption and performance fluctuations.

Therefore, achieving optimal efficiency requires coordinated optimization between transistor design, physical layout, and architecture.

Emerging device architectures, such as complementary field-effect transistor (CFET) architectures (vertically stacked NMOS and PMOS nanosheets), offer a pathway to achieving this goal by reducing logic area and wire length and improving electrostatic performance. Research shows that chip-level power consumption can be reduced by up to 30% using such approaches, extending energy-efficient miniaturization beyond traditional nanosheet technology.

These advances reinforce a key theme repeatedly emphasized in ISS: process innovation must now serve system-level efficiency goals, rather than individual device metrics.

Packaging as a fundamental technology

Perhaps the most profound shift in semiconductor innovation lies in the transformation of packaging technology from a supporting technology to a primary performance driver.

Advanced packaging technologies have overcome the limitations of photomask size, enabling integration and improving energy efficiency through high-density interconnects. Silicon interposers and short-distance chip-to-chip connections allow chipsets to communicate with bandwidths approaching those of on-chip metal interconnects, significantly improving energy efficiency compared to traditional board-level connections.

3D interconnect technologies further enhance efficiency. Hybrid bonding and through-silicon vias (TSVs) enable vertical interconnects, achieving up to three times the interconnect energy efficiency compared to traditional microbump connections.

These technologies are particularly important for AI workloads, as data transmission energy consumption accounts for an increasingly larger proportion of total system power consumption.

Power supply and thermal management have also become core design challenges. AI accelerators with power exceeding 1000 watts require the integration of voltage regulation, deep trench capacitors, and advanced thermal interface materials to maintain efficiency and reliability.

Thermal management directly impacts system-level power consumption, as increased temperature increases leakage current, resulting in a "thermal tax" on computing performance.

Figure 2 below illustrates the packaging innovations required for this extreme size expansion.

Interconnect, optics and system-level expansion

As AI clusters scale to thousands of accelerators, system interconnect efficiency becomes as important as chip-level performance.

At data rates exceeding 224 GT/s, electrical interconnects are approaching practical limits, driving industry interest in optical interconnects and co-packaged optics. Integrating silicon photonics with computational silicon offers a pathway to reduce power consumption for long-distance data transmission while increasing bandwidth and transmission distance (Figure 3).

Both Fuselier and Chandrasekaran emphasized that interconnect technology must be viewed as a strategic technology. Future performance improvements will depend on coordinated innovation in areas such as packaging, networking, and system architecture, not just faster computing engines.

Manufacturing complexity and economies of scale

The industry faces just as many technological and economic challenges. Currently, state-of-the-art wafer fabs require investments of nearly $20 billion to $30 billion, while process node transitions involve exponentially increasing complexity.

Chandraskaran describes modern semiconductor manufacturing as "operating with atomic precision." He emphasizes that "we are essentially controlling one atom at a time," highlighting the scale of engineering required to sustain innovation.

Meanwhile, supply chain complexity has expanded from wafers and equipment to various aspects such as materials, labor supply, and infrastructure constraints. The rapid development of artificial intelligence has exacerbated these pressures, as demand growth outpaces capacity growth.

A recurring theme in technical papers and keynote speeches is the necessity of ecosystem coordination. Energy-efficient AI architectures require collaboration among hardware manufacturers, software developers, and materials suppliers.

Shared standards and open ecosystems enable more focused rather than fragmented investment, accelerating time-to-market and reducing supply chain risks. Fuselier emphasizes that consensus around common specifications is crucial for efficiently scaling capacity and innovation. This collaborative approach extends beyond the technical level to talent development and community investment, ensuring the semiconductor industry's sustainability in the context of AI reshaping the global economy.

Source: Semiconductor Industry Observer

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