The shrinking size of devices necessitates increasingly smaller metal lines and dielectric gaps, making resistance, capacitance, and material stability the primary limiting factors.

In recent months, researchers from the University of Houston, Northwestern University (in collaboration with IBM), and the University of Edinburgh have reported material advancements targeting different aspects of this bottleneck: low-dielectric-constant interlayer dielectric materials, nanoscale interconnect conductors, and Group IV alloys for optoelectronic integration.

These three studies collectively demonstrate that, in addition to transistors, the materials of the circuitry and its surroundings are increasingly becoming decisive factors influencing the device's scaling potential.

Rethinking the trade-offs of dielectric properties

Researchers at the University of Houston have demonstrated a large-area two-dimensional covalent organic framework (COF) film with a reported dielectric constant of approximately 1.17 at 100 kHz. In contrast, conventional organosilicon materials with low dielectric constants used in advanced back-end processes typically have dielectric constants much higher than 2, and lowering the dielectric constant by increasing porosity sacrifices mechanical strength and breakdown reliability.

According to ACS Nano, the University of Houston research team synthesized covalent organic framework (COF) films using a liquid-liquid interfacial polymerization method, fabricating continuous thin layers and characterizing their electrical and thermomechanical properties. In addition to the ultra-low dielectric constant (K-value), the material exhibits a dielectric strength of approximately 3908 MV/m at room temperature and approximately 2100 MV/m at 300°C. The Young's modulus is approximately 3.4 GPa, and the density is close to 1.1 g/cm³.

This combination addresses a long-standing problem in back-end interconnect (BEOL) integration. Decreasing the dielectric constant by increasing porosity typically reduces breakdown strength and makes the film brittle during chemical mechanical polishing and thermal cycling. The reported COF film aims to reduce capacitance without relying on a high-porosity structure, while maintaining electrical and thermal stability at high temperatures.

Current research focuses on planar test structures, and integrating them into patterned interconnect stacks requires evaluation through plasma exposure, adhesion to barrier layers, and time-varying dielectric breakdown testing. Furthermore, extending the deposition process to conformal coating of trenches and vias remains an open question. Nevertheless, data suggest that polymer-derived framework structures may offer a novel approach to achieving dielectric constants below 2 without compromising reliability.

Shielding conductors other than copper

If capacitance is one side of the RC equation, then resistance is the other. As copper wire widths shrink to the nanometer scale, surface scattering and grain boundary scattering cause a sharp increase in resistivity. This effect has sparked interest in other conductors whose transport mechanisms are less sensitive to size constraints.

Northwestern University researchers, in collaboration with IBM, have developed a computational screening framework for identifying topological halfmetals suitable for nanoscale interconnects. The team evaluated the transport properties of candidate materials using the Wannier tight-binding model and simulations incorporating surface disorder and roughness, generating a dataset containing approximately 3,000 surface transport values.

The fundamental premise of this paper is that certain topological materials possess surface states capable of resisting backscattering. In sufficiently narrow wires, these surface channels can contribute a significant portion of the total conductivity, thereby mitigating the resistivity expansion observed in copper. Materials highlighted in this paper include TiS, ZrB₂, and nitrides such as MoN, TaN, and WN, with NbAs and NbP serving as benchmark materials.

Finally, this study establishes a screening method and ranks candidate materials for interconnect fabrication based on simulated transport indices confined to the nanoscale. Future research will focus on deposition compatibility, patterning, pad integration, and electromigration characterization. Furthermore, the contact resistance with conventional device layers will determine whether these materials can truly replace or complement copper in specific stacked layers.

Extended Ge-Sn phase space

Research at the University of Houston and Northwestern University focuses on improving electrical interconnect performance, while researchers at the University of Edinburgh are working to address the finite phase space problem in the optoelectronic applications of Group IV alloys.

In high-pressure experiments conducted at 9–10 GPa and temperatures up to 1500 K, the University of Edinburgh team synthesized a hexagonal Ge-Sn solid solution that is unattainable at room temperature and pressure. The resulting material has a P6₃/mmc structure and exhibits three polytypes: 2H, 4H, and 6H. Hexagonal symmetry was observed when the Sn content was below approximately 21 at%. Above this threshold, the system transforms into a cubic diamond structure.

Hexagonal germanium has been reported to possess direct bandgap characteristics, but its optical transitions may be weak. Introducing tin can expand the lattice and alter the electronic structure, providing a potential pathway for manipulating the optical properties of silicon-compatible material families. High-pressure synthesis demonstrates that these phases are stable and recyclable at room temperature and pressure, thus broadening the compositional selection range for group IV semiconductors.

While this work focuses on synthesis and structural characterization, further investigation is needed to quantify carrier mobility, optical gain, and defect density, and to explore thin-film growth routes compatible with wafer-level fabrication. If such materials can be realized at the device level, they could support on-chip photonic devices without the need for integration with group III-V compounds.

Source: Compiled from allaboutcircuit

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