SK Hynix previously showcased its latest 5-bit cell NAND flash memory technology at the 2025 IEDM conference in San Francisco. This technology splits a 3D NAND cell in two, increasing the bit level while reducing the required number of voltage states by approximately two-thirds, which the company says improves speed and endurance.

SK Hynix introduced its multi-site cell technology for five-layer cell NAND in its keynote address on May 18-5. The company has been developing this so-called 4D 2.0 technology since at least 2022. The idea is to bypass voltage state barriers, thus avoiding simply adding more than four bits (QLC) to the NAND cell.

NAND Store Charge

NAND cells store charge, which is read by measuring the threshold voltage at which the cell begins to conduct current. If the cell is conducting or not conducting current, it emits a binary state signal: on/off, open/closed, 1, or 0. In a 1-bit or single-level cell (SLC), only two voltage states are needed, but as the cell increases by one bit, the state number doubles.

• 1 bit, SLC = 0 or 1 – Represents two states and one threshold voltage.

• 2 bits, MLC = 00, 10, 01, or 11 – Four states, therefore three threshold voltages.

• 3 bits, TLC = 000, 001, 010, 011, 100, 101, 110, 111 – Eight states, therefore seven threshold voltages.

• 4 bits, QLC = 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 – 16 states, therefore 15 threshold voltages.

• A 5-bit PLC has 32 states: 00000, 00001, 00010, 00011, 00100, 00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100, 01101, 01110, 01111, 10000, 10001, 10010, 10011, 10100, 10101, 10110, 10111, 11000, 11001, 11010, 11011, 11100, 11101, 11110, 11111 – 31 threshold voltages.

Increasing the voltage state narrows the gap between states, reducing the detection margin. With each additional bit, the time required to program and read the cell content increases, and stored electrons leak over time, weakening the voltage state and gradually increasing the difficulty of bit level detection until it becomes unreliable. Furthermore, the increased number of bits accelerates cell wear.

Currently, QLC 3D NAND flash memory is commercially available, but PLC flash memory is not yet commercially available because the read reliability and durability of PLC cells are too low. However, PLC flash memory is highly attractive because it can increase the capacity of NAND chips (and consequently solid-state drives) by 25% compared to QLC technology. We can increase the capacity of solid-state drives by increasing the number of 3D NAND stack layers within each NAND chip, but this requires more complex semiconductor process steps.

If PLC technology can increase cell capacity with fewer and simpler process steps without increasing the stacking structure, while avoiding the speed and durability shortcomings of existing technologies, it will be extremely attractive to NAND flash memory manufacturers. SK Hynix believes they can achieve this by effectively dividing a NAND cell into two independent parts (or "bits"), each with fewer and more independent voltage states, and constructing the bit value by combining the values of the two bits.

The image below compares existing multilayer cell (MLC) technology with the multisite cell (MSC) concept as viewed from above:

Achieving this requires additional semiconductor process steps, such as dividing the elliptical cell in half, filling the gaps to form walls, and adding bit line connections to each half.

Each half-cell has six voltage states, which, when multiplied together, result in a total of 36 voltage states. These 36 states satisfy the 32 states required by PLC flash memory, with four states being ignored, as shown in the table below:

After both half-cells are erased (ERS state), the bit value is 11111.

Because each site has only six voltage states, the voltage gap between them can be larger, reducing electron leakage and shortening programming time. This also helps extend the cell's lifespan. The two halves of the MSC cell are read simultaneously, i.e., in series.

The company states that the read speed is 20 times faster compared to non-MSC PLC flash memory.

SK Hynix's engineering research paper

SK Hynix presented a semiconductor engineering research paper at the 2025 IEDM conference. The company has manufactured wafers with active devices and will investigate how to manufacture PLC MSC flash memory in a cost-effective manner. Other flash memory manufacturers, such as Kioxia, Micron, Samsung, and SanDisk, will also conduct similar research.

If an MSC half-cell is given 8 voltage states, then the entire cell will have 64 voltage states (8 x 8 = 64), sufficient for the needs of a 6-bit six-level cell (HLC). This cell can have comparable speed and endurance to existing TLC cells and 50% higher capacity than QLC chips.

Source: Compiled from blocksandfiles