Marvell today announced that it will showcase PCIe® 8.0 SerDes at its booth 904 at DesignCon 2026, held at the Santa Clara Convention Center in California from February 24 to 26. SerDes offers data transfer rates of 256 gigabits per second (GT/s).

As artificial intelligence workloads continue to drive a surge in demand for data center infrastructure, PCIe technology is evolving to provide higher bandwidth for in-chassis, in-rack, and cross-rack connections. The PCIe 8.0 specification, expected to be finalized in 2028, promises to offer twice the bandwidth of the PCIe 7.0 specification, with bidirectional bandwidth reaching up to 1 TB/s, thus supporting demanding applications including artificial intelligence, machine learning, high-speed networking, and other data-intensive workloads.

PCIe 8.0 specification

To prepare for the arrival of the PCIe 8.0 specification, hyperscale data center operators and cloud data center operators can now begin exploring pathways and developing strategies to restructure their infrastructure to fully leverage its advantages after the new specification's release. Marvell will be the first to demonstrate the PCIe 8.0 specification and its TE Connectivity AdrenaLINE Catapult connector at DesignCon 2026, aiming to help the industry break through the limitations of traditional copper interconnects and achieve scalable growth.

Marvell® Alaska® P PCIe 6.0 retimer and its PCIe 7.0 and PCIe 8.0 SerDes technologies enable low-power, low-latency, and low-error-rate transmission over copper and Fibre Channel, providing the scalability, energy efficiency, and high performance required for next-generation infrastructure to support the bandwidth demands of future artificial intelligence and data centers.

PCIe 8 draft released, bandwidth up to 1 TB/s

Following the recent completion of the PCIe 7.0 specification, the PCI Special Interest Group (PCI-SIG) has begun developing the next-generation specification. While consumer PCs typically lag behind the latest connectivity protocols by several years, alliance members can now get a head start on emerging technologies that will impact artificial intelligence, data centers, and other high-end IT workloads.

PCI-SIG members now have access to draft version 0.3 of the PCIe 8.0 specification, the first official description of the upcoming protocol's goals. PCIe 8.0 continues the steady progress of the past few years and is expected to provide eight times the bandwidth available to today's cutting-edge PC components. However, consumers will still need several years to see this new standard in practice.

A key goal of PCIe 8.0 is to continue the trend of doubling the total bandwidth with each generation. This pattern has continued from PCIe 1.0 to 7.0, and the alliance believes 8.0 will be no exception.

The main goal of PCIe 8.0 is to continue the trend of doubling the total bandwidth with each new generation of products. According to the specification:

PCIe 8.0 Specification Feature Goals:

• Provide a raw bit rate of 256.0 GT/s and bidirectional transfer rates up to 1.0 TB/s through x16 configuration

• Review new connector technologies

• Confirm that latency and FEC targets will be achieved

• Ensure reliability targets are met

• Maintain backward compatibility with previous generations of PCIe technology

• Develop protocol enhancements to increase bandwidth

• Continue to emphasize technologies for reducing power consumption

Currently, most consumer PCs use PCIe 3.0 or 4.0, supporting transfer rates of 8 GT/s and 16 GT/s respectively, achieving bandwidths of 32 GB/s and 64 GB/s on x16 lanes. The latest SSDs and graphics cards support PCIe 5.0, with transfer rates reaching 32 GT/s and up to 128 GB/s. Many PCIe 5.0 compatible SSDs now boast read speeds exceeding 10 GB/s.

The alliance released the final specifications for PCIe 6.0 in early 2022, achieving 64 GT/s and bandwidths up to 256 GB/s. Testing of the first SSDs using this protocol only began earlier this year, with a Micron storage expansion card achieving an impressive speed of 30.25 GB/s.

PCIe 7.0 doubles those figures again, reaching 128 GT/s and 512 GB/s, and its final specification was only recently released. Compliance with PCIe 7.0 is planned to begin in 2028, and a detailed FAQ was released earlier this month.

If development stays on track, the PCIe 8.0 1.0 specification is also expected to be available in 2028. At speeds of 256 GT/s, the upcoming protocol has the potential to break the TB/s barrier on bidirectional x16 lanes.

The development of PCIe 8.0 involves several additional goals. Achieving faster speeds may require exploring fiber optic connector technology while meeting latency targets and maintaining reliability. Developers are also working to reduce power consumption and ensure backward compatibility with earlier PCIe versions.

The PCI-SIG anticipates that PCIe 8.0 will play a crucial role in supporting demanding workloads such as artificial intelligence, machine learning, edge computing, quantum computing, hyperscale data centers, and applications in military, aerospace, and automotive sectors.

Source: Compiled from Marvell

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