On April 15, Elon Musk showcased one of the first samples of Tesla's AI5 hardware, which will power artificial intelligence applications in Tesla vehicles, Optimus robots, and future xAI data centers. 

According to Musk, the AI5 processor is about half the size of the AI4, uses industry-standard memory, but can be up to 40 times faster than the AI4 in certain situations.

"Congratulations to Tesla's AI chip design team on the successful tape-out of the AI5 chip," Elon Musk posted on Xbox One. "AI6, Dojo 3, and other exciting chips are in development. [...] Thanks to Taiwan Semiconductor Corporation and Samsung for their support in mass production of this chip! It will be one of the highest-volume AI chips ever."

Tesla AI5 processor

The Tesla AI5 processor module uses a small ASIC chip (according to Musk, about half the size of the photomask) surrounded by 12 memory packages from SK Hynix (likely GDDR6/7). The module uses an organic substrate, and the memory package markings are identical to industry-standard DRAM products. While the AI5's memory interface width is unclear, the 12 memory packages clearly indicate a fairly wide memory I/O interface. If it is indeed 12 GDDR6/7 memory chips, then the Tesla AI5 ASIC's memory interface is 384-bit. Depending on the type of memory used, the Tesla AI5's memory bandwidth could range from 768 GB/s to 1.536 GB/s. Specific performance figures for the AI5 have not been released, but Musk claims that in some cases, its performance is significantly improved compared to the AI5, up to 40 times faster.

"I think the Tesla chip team is designing a really great chip: by some metrics, the AI5 chip will be 40 times faster than the AI4 chip," Elon Musk said during Tesla's Q3 2025 earnings call. "Because we've phased out outdated hardware, we can actually fit the AI5 chip on half a photomask and have plenty of headroom for the wiring from memory to the Tesla accelerator, Arm CPU cores, and PCIe modules."

AI5 chips

While Musk claimed the AI5 chip was "tape-out complete" (meaning the final chip design had been sent to the photomask manufacturer), he actually demonstrated a manufactured processor marked "KR 2613," indicating the ASIC chip was packaged in week 13 of 2026. Musk also mentioned TSMC and Samsung's involvement in mass production, but it's unclear whether passive component manufacturers are involved in the AI5 processor's mass production. More likely, Musk was referring to TSMC.

Previously, executives from Tesla, SpaceX, and xAI stated that the AI5 would be manufactured by TSMC and Samsung foundries, but it's unclear which foundry produced the current samples. Assuming Tesla received the chip in March or early April and didn't need to re-make the PCB, the company could deploy the processor in 2027.

Perhaps the most noteworthy part of this announcement is that Tesla has clearly not abandoned the Dojo System-on-Wafer (SoW) processor for AI training; the Dojo 3 processor is under development. Last August, reports surfaced that the Dojo wafer-level processor project had been abandoned and the team disbanded. Indeed, according to Peter Bannon's LinkedIn page, the Tesla Dojo project leader retired last August. Elon Musk stated in July that AI6 and Dojo 3 might adopt a converged architecture (which we speculate is a converged instruction set architecture), allowing the company to unify its software stack and potentially eventually achieve hardware stack unification.

"I think Dojo 3 and AI6 are among the first converged architecture designs," Musk said on the July 23 earnings call. "Intuitively, we want to find a converged solution where the chips are essentially the same, like using two such chips in a car or Optimus system, and more on a server motherboard, like five to twelve chips on one motherboard, etc. This seems like a logical direction."

Source: Compiled from tomshardware

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