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Japan 2nm wafer fab

2025-08-01

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Japanese semiconductor manufacturer Rapidus released its 2nm process chip trial samples for the first time on the 18th, striving to achieve mass production in 2027. Professor Seok Joon Kwon of Sungkyunkwan University in South Korea is not optimistic about the development of Rapidus. He posted a nearly 10,000-word article on Facebook to complain and suggested that it could find a buyer to acquire it, and the first choice is TSMC. If no one acquires it, it might be a good idea to consider cooperation between Japan and South Korea.

Rapidus Progress

Rapid construction

One of the two-way strategies that the Japanese government is ambitiously pursuing to revitalize the semiconductor manufacturing industry is the Rapidus project. According to recently disclosed data, Rapidus started construction of its first wafer fab, the IIM-1 wafer fab, in the Chitose area of Hokkaido in September 2023. It took only 8 months, or April 2024, for the fab's framework, clean room and basic equipment to be completed.

Equipment introduction

Meanwhile, Rapidus introduced ASML's EUV lithography equipment in December 2024, the first mass production wafer fab in the Japanese semiconductor industry and the fifth in the world (the equipment installation ceremony was held on December 18).

Trial production

Even more surprisingly, they announced the launch of the pilot line on April 1, 2024, less than four months after the equipment introduction, even though they had almost no experience in operating ArFi DUV lithography technology, let alone EUV. Even more surprisingly, they reported that they successfully completed the first GAAFET wafer-based electrical characteristic test (i.e., the minimum proof-of-concept signal that the device can work properly) in mid-July, just three months after the pilot line started trial production on April 1, 2025.

Challenge doubts

Speed doubts

From Rapidus' recent disclosures, we need to focus on the speed of completion of the three tasks they claim to have completed. The first is the speed of completion of the fab. It took only 8 months from groundbreaking to completion. This is more than three times faster than the usual two years. The second is the speed of process stabilization after the introduction of EUV. It took only 100 days from introduction to the pilot line. Third, after the EUV test run, it took only 100 days to produce the first test wafer. To compare the execution speed of these processes, we compare it with TSMC or Samsung Electronics' foundries. Even after the equipment arrives at the fab, it takes at least half a year for the EUV lithography machine to be installed and stabilized. When TSMC or Samsung Electronics introduced EUV in the process of adopting the 3nm process, it took at least 30 to 50 weeks, and S Company even took more than a year.

Process Differences

Of course, it is difficult for us to fully believe these claims. One hint we can get from the disclosed information is that their foundry process adopts a single-wafer process, which is different from TSMC or Samsung Electronics' foundries. 

This is different from other companies that mainly adopt mass production methods. For example, if other companies have mass production lines like Hyundai or Toyota, then Rapidus is like the process of hand-making supercars such as Lamborghini or Ferrari, one by one. This metaphor is actually very appropriate, because supercars like Lamborghini or Ferrari can maintain a unit price nearly 10 times higher than that of general mass-produced cars, which makes this kind of hand-made manufacturing possible. 

Of course, no one can guarantee that Rapidus Fab will definitely be able to manufacture Lamborghini-level supercars. If the fab produces in a single-wafer manner, the EUV lithography data obtained is likely to be qualitatively different from the data obtained by mass-producing multiple wafers and at the same time, because mass production can maintain a consistent quality level. 

In other words, this means that only by extracting suitable data from the first few wafers of the exposure process can the process be declared successful. This does not mean that this method is dishonest. Of course it can be done. 

However, the problem with this strategy is that it is far from the "mass production" model that Rapidus originally envisioned. In other words, Rapidus' public information is likely to be propaganda for the sake of technology marketing.

Data missing

When the Rapidus project was first announced, many experts were skeptical because the 2nm process targeted by Rapidus adopted the "leapfrog method" and skipped all the "step-by-step" technologies between the discontinued 18nm and below processes in Japan and the 2nm process. At this stage, who would refuse to adopt such a breakthrough method that can instantly skip more than 10 steps?

If it can, Chinese wafer foundries may also want to do this, and they have done it, and even more. However, there is a reason why Rapidus and other later wafer foundries must go through the process of accumulating experience from mature processes, even if it takes some time. Even for DUV, most processes are not much different, especially managing yield by repeating the LE process many times in a wafer batch, which is a trick that is difficult to master without sufficient experience. The various stages such as 18nm, 14nm, 10nm, 8nm, 7nm, 6nm, 5nm, 4nm and 3nm are not only strategies to ensure progressive technology, but also crucial stepping stones.

They are the technical base camps that must be secured to move to the next stage. Especially in single-digit nanometer processes, not only the transformation of lithography technology, but also the transformation of materials including metal oxides are taking place at various stages. In this process, it is necessary not only to meet whether the process is simple and feasible, but also to optimize chip performance and the process required by fabless customers at the same time. Rapidus said that they will skip nearly ten intermediate links instead of one or two, which is not entirely reasonable. They have reached an agreement with IBM to introduce GAAFET licensing, and it is reported that they have also discussed some degree of process cooperation with ASML and IMEC. However, it is not clear how they will obtain the technical know-how that must be mastered independently in these processes, and whether they have enough experts to bring it to a high enough level in a short time.


In the information disclosed by Rapidus, they are said to have confirmed the electrical characteristics of the wafers that have completed the initial EUV process, but the specific data has not yet been disclosed. If they really have enough technology, they should disclose the electrical characteristics of the wafer in detail (such as threshold voltage, leakage current, drive current, subthreshold slope, switching speed, power consumption, capacitance, etc.), and strategically, it is also correct to disclose the EUV exposure process quality level data that everyone cares about, such as LER/LWR of the pattern, CD/CDL uniformity, overlay uniformity, exposure power and dose. This is because they can advertise their fab process capabilities to potential fabless customers as being competitive enough. However, Rapidus has not disclosed detailed data yet, nor has it mentioned the type of specifications, let alone exposure process data. 


Of course, if everything goes according to plan, Rapidus may announce detailed specifications at the VLSI Technology Symposium scheduled for December 2025, but the detailed specifications are still shrouded in mystery. 

The same is true when searching for patents. If you search Rapidus's literature on the patent search portal, you will find some process technology patents, but most of them only claim the right to 2nm process integration, and the description of specific process parameters (gate stack configuration, photolithography mask design, oxide material, etc.) cannot be confirmed.

Despite the announcement of the Rapidus project with impressive fast wafer builds, exposure process stabilization, and prototype wafer production, it is still difficult to change the initial judgment that it is difficult to ensure sustainable development as a wafer foundry from a business perspective. The biggest reason is their recently announced single-wafer-oriented production strategy with great confidence.

Considering the relatively small scale of their wafer fabs and the fact that the customer ecosystem has not yet been fully formed, this is not difficult to understand.

However, as mentioned earlier, the single-wafer process like hand-building a supercar is different from the batch methods of other companies.


Source: Content from Semiconductor Industry Observation


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