Intel compared its EMIB interconnect solution to traditional 2.5D technology and demonstrated its advantages in designing advanced packaged chips.

Intel's EMIB technology has been applied to a variety of chips, most of which are Intel's own products. They have adopted this interconnect solution in Ponte Vecchio, Sapphire Rapids, Granite Rapids, Sierra Forest, and the upcoming Clearwater Forest series.

Intel has demonstrated how it is expanding its advanced packaging capabilities to produce next-generation chips, including both its own and those manufactured for its foundry customers. The company highlighted large-scale packaging, all utilizing EMIB and several other proprietary packaging technologies. All of these chips will be advanced chip solutions designed specifically for data centers, comprising multiple chipsets connected via EMIB interconnect technology.

Competitors (such as TSMC) have advanced packaging technologies based on 2.5D and 3D packaging. Unlike EMIB and others that use smaller interconnect bridges, TSMC's 2.5D packaging uses a silicon interposer between the chip (chipset) and the package substrate. Interconnects are achieved through a series of wires located inside the silicon, called TSVs (Through Silicon Vias). These wires are used to connect multiple chips.

Intel points out that 2.5D packaging technology has some drawbacks. First, it requires additional costs for the silicon die used solely for interconnecting wires; second, the larger the chip size, the higher the cost of the packaging solution, as the use of TSVs (Through Silicon Vias) increases design complexity and reduces yield.

This technology also has limitations in terms of the maximum size achievable with 2.5D processes. This results in insufficient flexibility in chip combination, making it impossible to mix and match various computing and memory chips.

EMIB technology eliminates the need for a silicon wafer between the chip and the package. These small bridging structures are embedded within the substrate and can be installed wherever two chips need to be connected. EMIB technology has been around for a while, so it's not exactly new, but a brief review of the technology itself is worthwhile. There are two main variants of EMIB, detailed below:

EMIB 2.5D

Embedded Multi-Chip Interconnect Bridge 2.5D.

• An efficient and cost-effective method for connecting multiple complex chips.

• 2.5D package for logic-logic and logic-high bandwidth memory (HBM).

• EMIB-M uses MIM capacitors in the bridge circuit. EMIB-T adds TSV packaging to the bridge circuit.

• Silicon bridges are embedded in the package substrate for shore-to-shore connections.

• EMIB-T simplifies IP integration in other package designs.

• Simplifies the supply chain and assembly process.

• Production proven: Mass production using Intel and external chips has been underway since 2017.

EMIB 3.5D

Embedded multi-chip interconnect bridge 3.5D and Foveros are integrated in a single package.

• Supports flexible heterogeneous systems employing multiple chips.

• Ideal for applications requiring the combination of multiple 3D stacks in a single package.

• Intel Data Center GPU Max Series SoC: Utilizing EMIB 3.5D technology, it creates Intel's most complex heterogeneous chip to date in mass production, boasting over 100 billion transistors, 47 active chip cells, and 5 process nodes.

Therefore, in terms of advantages, Intel's EMIB advanced packaging solution not only offers greater flexibility in chip layout but also supports 2D and 3D expansion, which is impossible with 2.5D packaging methods. Intel lists three key advantages of EMIB technology:

• Normal packaging yield range

• Cost-saving opportunities

• Simple design

As Intel increases its investment in its foundry business and seeks greater attention for its future technologies, such as the 14A chip, advanced packaging solutions will become crucial. Improvements to its EMIB chips, such as the "T" package and Foveros package, have attracted the attention of numerous industry giants, intensifying competition in the chip manufacturing industry, which has previously been dominated by TSMC. Intel's ability to successfully launch the 14A chip and usher in a new era of advanced chip manufacturing in the United States depends on its determination.

Intel showcases its next-generation, scalable packaging capabilities

Previously, Intel showcased its packaging capabilities with a multi-chip product utilizing 18A/14A node chips, Foveros 3D, and EMIB-T technologies.

These technologies will set the standard for next-generation chips in high-performance computing, artificial intelligence, and data centers. Intel's advanced packaging solutions will also intensify competition with TSMC's CoWoS solution, which has also launched a 9.5-inch photomask packaging solution (CoWoS-L) using the A16 process node and integrating more than 12 HBM4E chips.

Here are some of the key technologies Intel will use to build its next-generation computing giant:

• Intel 14A-E: Breakthrough logic using RibbonFET 2 and PowerDirect.

• Intel 18A-PT: The first chip with rear-mounted power supply, improving logic density and power reliability.

• High-performance top-level chip: Next-generation performance, density, and performance per watt are all improved (Intel 14A/14A-E process nodes).

• Foveros Direct 3D: Precision 3D stacking using ultra-fine pitch hybrid bonding.

• EMIB-T (Embedded Multi-Chip Interconnect Bridge): The next-generation EMIB adds TSV for higher bandwidth and greater chip integration.

• HBM Protocol Support: Seamless support for the latest and future HBM standards (HBM4/HBM5/HBM-Next).

• >12x Lithography Line Scalability: The architecture breaks through the limitations of traditional lithography lines.

In the video released by Intel, the company showcased two advanced packaged chip solutions. These are clearly concept designs, but the designs themselves are the highlight. One chip features four compute units and 12 HBM memory sites, while the other has 16 compute units and 24 HBM memory sites. Furthermore, the number of LPDDR5X controllers has doubled, reaching as many as 48 in larger solutions.

This chip includes a computing substrate manufactured using 18A-PT process technology. This substrate houses SRAM, similar to the manufacturing process of Clearwater Forest. Clearwater Forest, manufactured using the 18A process node, integrates 576 MB of L3 cache in its three-cell substrate design. Since Clearwater Forest's substrate is manufactured using Intel's 3 process technology, we can expect Intel 18A-PT to further optimize and increase the amount of SRAM in future chips.

Above the base chip are the main computing chips, which may contain an AI engine, CPU, or other IP. These chips are manufactured using Intel's 14A or 14A-E process and are connected to the base chip through Foveros 3D packaging solutions to form a 3D stacked structure.

Multiple chips are interconnected via EMIB-T interconnect technology and further interconnected with the memory solution. The top-level chip shown in the diagram uses 24 HBM memory sites, which can be modern HBM standards such as HBM3/HBM3E, or future standards such as HBM4/HBM4E or HBM5. A single package can accommodate up to 48 LPDDR5x controllers, thereby significantly improving memory density for AI and data center workloads.

Intel also stated that they have developed a very diverse ecosystem engagement program and work directly with industry partners to accelerate time-to-market and enhance supply chain resilience.

This advanced packaging chip demonstration was clearly aimed at external customers, showcasing Intel's products, particularly the advantages of its 14A process node, which is designed for third-party clients. Intel had previously stated that the 18A process node was primarily for internal products, but the 14A node has attracted more customer attention. With this advanced packaging solution, Intel appears to have secured a place in the foundry market.

Now, the only thing we need to focus on is the actual products and confirmation of which products and major manufacturers will use Intel's foundries. While there are some scattered hints, nothing is certain yet. We should remember that Intel has consistently been a leader in advanced packaging. Their previous chip, Ponte Vecchio, was an engineering marvel, but due to numerous delays caused by yield issues, it ultimately didn't achieve great success, and several Intel projects, including Falcon Shores, were cancelled.

The company is making a strong comeback with Jaguar Shores and the highly anticipated Crescent Island GPU (for artificial intelligence), but at the same time, their real test lies in securing orders from third parties, as the company's 14A technology is crucial.

Source: Compiled from wccftech