The growing storage demands at the edge and in the cloud are driving the increasing need for higher-capacity flash memory across a variety of applications.

3D NAND flash memory is released every 12 to 18 months, boasting a product cycle and performance improvements far exceeding most other semiconductor devices. Each new generation delivers 50% faster read/write speeds, 40% higher bit density, lower latency, and greater energy efficiency.

3D flash memory manufacturers maintain this astonishing production rate by stacking and connecting memory cells, utilizing tiny, deep channels. These channels become smaller and deeper with each new generation. A groundbreaking cryogenic etching technology enables the drilling of billions of channel holes, each 10 micrometers deep, with near-vertical apertures, within openings of only 100 nanometers. In an industry that prioritizes energy efficiency and sustainability, these innovative etching tools aim to reduce energy consumption to half that of previous cryogenic solutions while reducing carbon emissions by more than 80%.

A key challenge in NAND flash memory etching is ensuring the vertical profile of the channels from top to bottom while maintaining a reasonable etching rate. Modeling plays an increasingly important role in optimizing process formulations to ensure consistent vertical profiles, avoiding critical dimensional deviations, bending, and shape distortion within the memory holes. Even with limited data, artificial intelligence can help optimize the contours of these features. These memory contours are crucial because their uniformity directly impacts NAND flash memory performance, a key metric for performance metrics such as read/write speeds and programming/erasing efficiency.

Major manufacturers of 3D NAND chips include Samsung Electronics, Western Digital, Kioxa (a Toshiba subsidiary), and SK Hynix. By stacking more and thinner alternating layers of silicon dioxide and silicon nitride (ON), they are able to increase the number of word lines by 30% in each generation of devices. Then, using deep reactive ion etching (DRIE) technology, billions of high aspect ratio cylinders (depth-to-width ratio exceeding 50:1) are etched onto the chip.

The DRIE reactor preferentially directs ions vertically, enabling parallel structures for deep trench isolation, through-silicon vias, MEMS cavities, and other vertical structures. In NAND flash memory, even extremely small atomic-level deviations in these features can degrade the device's electrical performance, leading to yield and performance degradation, and potentially affecting its reliability.

In a hole with a depth of 10 micrometers and a diameter of 100 nanometers, the allowable profile deviation is only 10 nanometers. "So if you consider a 10-nanometer profile deviation as a function of depth, then that's less than 0.1% profile deviation, which is really impressive," said Tae Won Kim, Vice President of Global Etching Products at Lam Research.

How can 3D NAND be expanded?

3D NAND chip manufacturers are scaling their devices using three key methods (see Figure 1). Flash cells can be arranged more closely (expanding in the x and y directions) or stacked using vertical interconnects. Since the industry transitioned from 2D NAND to 3D NAND around 2014, flash manufacturers have primarily used a vertically oriented construction approach, placing logic circuitry below the memory array to further reduce size (called under-array, or CUA). Chip manufacturers are also increasing the number of bits per cell without increasing area, scaling from single-bit to 4 bits per cell (four-layer cells) and higher, which increases the number of voltage states.

Figure 1: NAND flash memory achieves scaling by reducing cell pitch and size, stacking word lines, and increasing the number of bits per cell.

How did we get to this point?

Competition among NAND chip manufacturers is fierce, with each striving for exceptional uniformity and repeatability at every manufacturing step. This section showcases memory hole channel etching. Other important NAND high aspect ratio etching processes include: slits: etched areas used to isolate word lines, ensuring proper electrical functionality; multilayer contacts: holes connecting different metal wiring layers; and staircases: connections for accessing word lines within each layer (see Figure 2). After the vertical channel etching process, oxide layers, trap layers, and polysilicon channels are deposited along the sidewalls of the holes. This structure is often referred to as a "hollow powder channel."

Figure 2: Schematic diagram of a three-dimensional NAND gate-all-around architecture, showing a series of vertically arranged charge trap cells, using an oxide-nitride-oxide (ONO) gate dielectric, and a limited number of word lines.

In most NAND products, vertically aligned charge-trap cells replace the floating-gate (FG) transistors located above the source/drain. While both devices operate similarly, the charge-trap cells reside within a nitride layer deposited between the gate oxide layer (source and drain), essentially functioning as a vertical MOSFET device with an internal silicon nitride trap layer.

After the cell array is complete, chip manufacturers typically fabricate a second or stacked layer before stringing them together. "However, ensuring consistent diameters between these approximately 30µm thick stacked layers increases process complexity and cost, posing challenges to high-stack deposition and high-aspect-ratio etching processes," notes Sana Rachidi, Senior Integration Researcher on the imec Memory Process Integration Team.

While multi-layer short-layer structures can alleviate the burden on high-aspect-ratio etching equipment, they also increase cost and complexity, especially when multiple memory vias in the first layer need to be aligned with those in the second layer for subsequent interconnection. This necessitates a trade-off between the need for aligned short-layer structures and improved etching performance to etch deeper areas in the ON stack.

Currently, NAND flash memory suppliers are packaging multiple memory cells into a single-layer structure as much as possible before building a second layer. "Another trend is to optimize the peripheral CMOS circuitry on different wafers and then use hybrid bonding technology to connect it to the stacked layers of the memory array," Rachidi said. "To control the ever-increasing processing costs, they are also doing further scaling in the vertical direction, known as Z-axis pitch scaling."

Why is a low-temperature process necessary?

In traditional reactive ion etching (RIE) processes, the etching rate gradually decreases as material within the microvias is removed. In the 2010s, etching equipment manufacturers began exploring cryogenic processes (0°C to -30°C) to improve the productivity of RIE systems and enhance vertical etching performance by combining cryogenic processes with novel chemical methods.

By maintaining a low wafer temperature, high-energy fluorine and oxygen ions can effectively remove nitride layers and their associated impurities. "Lower temperatures suppress unwanted sidewall etching while enhancing ion mobility and bombardment," says Kim from Lam Research. This ultra-low temperature is achieved by using a cooler on the etching platform and helium cooling of the wafer.

From a chemical perspective, the higher etching rate stems from enhanced surface diffusion and physical adsorption of neutral materials. Importantly, process engineers need to control polymer formation at the top of the vias, as polymers can hinder ion flow to the bottom of the feature. "The aperture profile is controlled by precisely managing the wafer temperature and gas chemistry, leveraging the shift in the adsorption mode of neutral substances on the etched sidewalls from chemisorption to physisorption as temperature changes," Kim explained.

The required etching depth is constantly increasing. Yoshihide Kihara and colleagues at Tokyo Electron estimate, "For future chips with more than 400 layers, to maintain the current 2-layer stacked structure, the etching depth of each memory channel aperture needs to be at least 8µm."

This new chemical method can both increase etching rate and aperture depth while reducing carbon emissions. Tokyo Electron adds, "By using HF gas for etching, the partial pressure of conventional CF gas can be significantly reduced, resulting in an 84% reduction in greenhouse gas carbon emissions compared to first-generation cryogenic processes." The company also found that a small amount of phosphorus-containing gas (PF₃) can act as a catalyst, promoting the reaction between HF and SiO₂, thereby increasing the etching rate at lower temperatures.

The need for cryogenic etching technology is very clear. Kim points out that Lam Research has already installed 1,000 cryogenic etching chambers in its wafer fabs used for 3D NAND applications.

Reactive ion etching (RIE) can be performed using two types of reactors—capacitively coupled plasma (CCP) and inductively coupled plasma (ICP). ICP is generally more common because its two electrodes can independently control ion energy and density, while the radio frequency bias power accelerates the injection of active ions into the etched holes.

Many suppliers of RIE equipment exist, including Applied Materials, Plasma-Therm, Oxford Instruments, and Sentech Instruments, but Lam Research and Tokyo Electron (TEL) are the leading companies in high-volume production of cryogenic etching equipment. TEL launched its first cryogenic etching machine in 2023, while Lam Research launched its third-generation cryogenic etching machine in July 2024. Kim from Lam Research notes that these three generations of reactors utilize three different chemical systems. (Lam Research did not disclose the specific gases currently used.) Another key element of successful etching is the photolithography and etching mask used to form the holes and slots. Chip manufacturers first pattern the hard mask using a thick amorphous carbon hard mask (deposited via chemical vapor deposition) and then spin-coating glass and photoresist onto it. This thick mask protects the ON/ON/ON areas that need to be preserved during the etching process.

Lam Research also utilizes plasma pulses to switch between etching and passivation modes. Byproducts of the etching process are important because they passivate the sidewalls, preventing structural bending. The aspect ratio of vertical channel etching is already close to 70:1; transitioning to an aspect ratio of 100:1 will be more challenging to control.

Contour control, artificial intelligence and etching process

Modeling is playing an increasingly important role in improving manufacturing process outcomes. When developing etching processes to optimize NAND vertical channel (VC) etching, it's worth noting that there are over 30 adjustable etching parameters, including temperature, gas flow rate, power, process time, and more.

An Acer engineering team led by Cheng-En Tsai has proposed an AI-based approach to optimize the etching profile in vertical channel (VC) structures, thereby minimizing VC profile shape distortion. Unlike many AI-assisted modeling computations built using large, diverse datasets, the Acer team utilized data from 25 processed wafers (including wafer centers, middle sections, and edges) to optimize the etching process, thereby reducing critical dimension (CD) variations. This approach reduces process development costs and time.

Tsai and colleagues report, "One of the key challenges facing the semiconductor industry is minimizing wafer consumption as early as possible in process development, as this is crucial for reducing costs and accelerating product development." The AI program was able to optimize 33 etching parameters, thereby reducing variations in top CD, bow CD (widest point), CD distortion, and CD stripe intensity.

Acer's AI-assisted tuning method's core strategy involves fine-tuning a pre-trained Transformer model based on a comprehensive dataset. This fine-tuning process applies machine learning algorithms to small datasets derived from actual wafers and DOE slicing. "By inputting the predicted etching parameters into the model, the final VC profile is obtained, enabling the system to accurately simulate and predict VC structures," the Acer team emphasized the role of domain knowledge. "To improve the accuracy of model predictions, we set some preset parameters with specific constraints based on expert knowledge in the domain. This step is crucial for optimizing the model output and ensuring that the predictions match practically feasible etching conditions." Using transmission electron microscopy (TEM) measurements of bevel cutting at depths of over 10 in the vertical channel (VC), changes in the critical dimension (CD) were recorded, and optimized values for 33 etching parameters were determined through machine learning (ML). "By creating high-precision etching profiles, this method not only improves the quality of etched structures but also helps the semiconductor industry significantly reduce costs. Leveraging advanced optimization techniques, the AI-assisted tuning approach ensures that the final vertical channel structure exhibits superior performance in minimizing shape distortion and maintaining tight control over critical dimensions."

Most importantly, the new process formulation reduces feature distortion, which is directly related to NAND performance and reliability. "In the initial process, when VC shape distortion is severe, the threshold voltage suddenly rises, indicating performance instability during 3D NAND programming." The AI-assisted etching process completely eliminates this threshold voltage anomaly, thus achieving predictable and optimized device performance.

Are there risks to future miniaturization?

To continuously increase the number of ON layers in each generation of products, reducing the z-axis spacing between word lines (current devices have a z-axis spacing of approximately 40nm) seems reasonable. However, researchers at imec warn that as NAND flash memory manufacturers continue to shrink dimensions using existing materials, two physical problems arise—lateral charge migration and inter-cell interference.

Charge migration and signal interference can lower threshold voltage, increase subthreshold swing, reduce data retention time, and increase program/erase voltage. The imec researchers stated, "As word line layer thickness is further reduced, the gate length of the charge-trapping transistor also shortens accordingly. Therefore, the gate's control over the channel gradually weakens, and electrostatic coupling between adjacent cells increases. In addition to inter-cell interference, the shrinking of memory cells in the vertical direction also leads to lateral charge migration (or vertical charge loss). Charge trapped within the SiN layer tends to migrate through the vertical SiN layer, thus affecting data retention time." One process improvement that can suppress inter-cell interference is to replace the oxide dielectric between word lines with air gaps made of a low-dielectric-constant material (low k-value). In fact, air gaps have previously been used for this purpose in two-dimensional NAND devices. However, introducing air gaps in vertical structures is significantly more challenging than in planar structures.

Imec recently devised a repeatable air gap scheme that involves recessing the inter-gate oxide layer before depositing the ONO stack. "The introduction of the air gap allows for self-alignment with the word lines, enabling precise control over its position and providing a scalable solution." Researchers and manufacturers will continue to explore this and other schemes to further shrink the size of 3D NAND.

in conclusion

Low-temperature etching is a key development in reactive ion etching (RIE) processes, enabling the formation of extremely deep and thin cavities in 3D NAND devices for vertical contacts, slots, stepped contacts, and peripheral contacts. Chip manufacturers are optimizing over 30 etching parameters to ensure minimal variation in the vertical profile of the top-to-bottom critical dimension (CD).

As this highly challenging technology becomes more widely adopted, process simulation and AI-assisted design can play a significant role in formulation optimization without running hundreds of development wafers. This can save costs and shorten time-to-market. Therefore, the industry may increasingly rely on virtual manufacturing for these and other critical manufacturing steps.

Source: Compiled from semiengineering

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