Jim Handy of Objective Analysis and Jawad Nasrullah of Palo Alto Electron made predictions at last week's Chiplet Summit, outlining the future direction of the Chiplet market and why Chiplet is needed to accelerate the development of AI.

Handy points out that the development from multi-chip modules (MCMs) in the 1990s to multi-chip packages (MCPs) in the mid-1990s, and then to NAND flash stacking, stacked chips, large chips (such as Xilinx's sliced FPGAs around 2011), hybrid processes (such as AMD's I/O chips, with the core complex located in the center), HBM using TSVs, hybrid bonding (initially used by companies like YMTC and Sandisk for CMOS image sensors), and AMD's VCache technology. But are all these chiplets?

Figure 1. In which fields is Chiplet currently used?

Chipplet Design

For the purposes of this demonstration, a chipplet design is defined as multiple chips within the same package that communicate with each other using signals optimized for in-package communication (this excludes the first three chips in Figure 1 above).

Handy lists nine compelling reasons to use chipplets:

1. Due to reticle size limitations, designs that are too large to fit on a single chip need to be split across multiple chips.

2. Larger chips have lower yields, making it more economical to use more and smaller chipples.

3. Mask costs for large designs (close to the photomask) at advanced process nodes can range from $30 million to $50 million.

4. Chiplets allow chip manufacturers to limit the use of expensive process nodes to where it is profitable.

5. They make it easier to generate more SKUs.

6. They can accelerate time-to-market with lower non-recurring engineering costs.

7. They allow for the mixing of different wafer technologies, such as memory and logic circuits, or optics.

8. Some technologies do not shrink with process node shrinking (SRAM). 9. Chiplet can save energy.

Figure 2. Relationship between yield and die area

Xilinx's use of multiple chiplets to fabricate large FPGAs is an example of efficient large-chip manufacturing. Figure 2 shows the yield curve calculated using the Bose-Einstein curve set. Large single-chip yields are the lowest, making chiplets a more cost-effective solution for large-scale applications, especially AI applications for large data centers.

Figure 3. Examples of large monolithic chips and small chiplets

Handy points out that the table in Figure 3, presented by AMD CEO Lisa Su, aims to illustrate how a 4-chip design can offer a larger chip area and a better solution at only 59% of the cost. Using expensive process nodes only when there is a clear advantage also helps reduce costs. Figure 4 (below) shows that SRAM size has essentially stopped shrinking after the 5nm process node.

Figure 4. SRAM cells have stopped scaling.

Based on the data above, if SRAM can be placed on lower-cost, older-process chips and connected using hybrid bonding technology, then there is no reason to occupy valuable area in advanced processes to manufacture SRAM. AMD's Zen 5 and Zen 5c designs are examples of using different core chips and/or different numbers of core chips to more economically produce new SKUs.

DRAM process chips and CMOS logic substrates

HBM is one example of using different wafer technologies, combining stacked DRAM chips with CMOS logic substrate chips. CMOS image sensors (CIS) are another example. More types of memory will emerge in the future - MRAM, ReRAM (resistive), and FRAM (ferroelectric), increasing application possibilities because they do not limit the process technology of other parts of the design.

Capacitors are the bane of speed and low power consumption. For processors, everything looks like a capacitor—memory slots, buses, DRAM, and expansion channels all require a significant amount of energy to oscillate these signal lines. Signal lines routed on an interposer have better (lower) capacitance characteristics.

Figure 5. Economies of scale reduce costs

Economies of scale reduce costs. Competition between DRAM and NAND spurred the development of SSDs. The same phenomenon also propelled the growth of UCIe, a byproduct of increased scale and reduced I/O design costs.

Figure 6. Nvidia's data center revenue surges

Figure 7. Are all these AI expenditures sustainable?

Nvidia's data center revenue is soaring, with capital expenditures on hyperscale data centers exceeding $70 billion in 2025, roughly double that of 2024. Artificial intelligence spending is also accounting for a larger share of hyperscale data center revenue, roughly doubling its share over the past five years.

Handy points out that chiplet technology itself doesn't create new markets, but it is driving the development of artificial intelligence. Chiplet is an enabling technology, and he expects hybrid bonding technology to become a very important one.

The report concludes by predicting that the chip market will reach $600 billion by 2031, roughly equivalent to total semiconductor revenue in 2025. Therefore, driven by massive capital expenditures on AI systems, chip market penetration will continue to grow.

Source: Compiled from semiengineering

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