As the commercialization of 20-layer high-bandwidth memory (HBM) stacking technology draws ever closer, discussions about relaxing international semiconductor standards are intensifying.

Industry insiders revealed on the 8th that a key topic at the recent Joint Electron Devices Engineering Committee (JEDEC) meeting (JC-42) in Nashville was relaxing the height requirement for HBM products to 800 micrometers or higher. The JEDEC March meeting aimed to refine last year's draft and coordinate key next-generation standard technologies for this year.

As the number of stacked layers increases, the standard height of HBM has been continuously adjusted. Previously, the international standard had been relaxed from 725 micrometers to 775 micrometers, but further relaxation to 800 micrometers or higher is under consideration to address the physical limitations of 20-layer stacking processes.

Backside grinding process

To meet the existing 20-layer stacked 775-micron standard, a back-grinding process is required to process individual DRAM chips to be extremely thin. This process increases the risk of wafer damage, leading to a significant drop in overall yield. As its largest customer, NVIDIA has recently prioritized "supply stability" over performance metrics, further fueling this discussion. NVIDIA is considering a "dual-channel" approach, allowing the parallel use of the lower-end (10.6Gbps) version of the next-generation HBM4 alongside the existing 11.7Gbps version. This trend of specification reduction has also sparked discussions about relaxing physical thickness specifications.

Relaxing thickness specifications could provide domestic memory manufacturers with a technological buffer. For example, SK Hynix could extend its flagship process—Major Reflow Molding Underfill (MR-MUF)—to 20-layer products. A broader relaxation of standards could potentially delay the rollout of expensive hybrid bonding equipment, thereby improving profitability.

Samsung Electronics, which has entered HBM4 mass production, is also expected to improve its effective yield by relaxing specifications. This is because ensuring sufficient physical space reduces process complexity, thus enabling stable production response.

This discussion on deregulation is expected to be a key factor in determining HBM market leadership over the next three years. If Nvidia participates in the forum in San Jose on May 13th, the deregulation proposal could be approved. If the proposal is finalized at the Sapporo meeting in June, Japanese manufacturers will have the technological foundation to mass-produce 20-layer products using existing process systems.

However, some believe that deregulation is merely a stopgap measure, not a fundamental solution.

An industry insider explained, "Product height can be adjusted using conventional methods, but as the number of layers increases, the heat generated internally becomes more difficult to dissipate."

How will the bonding technology between Samsung and SK develop?

HBM is a next-generation memory technology that vertically stacks multiple DRAM chips and connects them with tiny bumps.

Previously, the standard thickness of HBM before HBM3E was 720 micrometers, but HBM4 increased the thickness to 775 micrometers. This is primarily due to the increased number of DRAM stacking layers in HBM4 (12 and 16 layers respectively) compared to previous generations (8 and 12 layers).

Furthermore, the industry is discussing relaxing the standard thickness for next-generation HBM chips (such as HBM4E and HBM5), which use 20-layer stacked DRAM. The currently discussed thickness ranges from 825 micrometers to over 900 micrometers. If a standard of over 900 micrometers is ultimately established, it is expected to represent a significantly larger increase than previous generations.

An industry insider stated, "JEDEC must establish key standards one to one and a half years before product commercialization, therefore, discussions about the thickness of next-generation HBMs are actively underway." He added, "Thicknesses of 900 micrometers or more are already being discussed."

JEDEC is an international semiconductor standards organization responsible for setting standards for semiconductor products. Memory companies including Samsung Electronics, SK Hynix, and Micron, as well as major global semiconductor companies such as Intel, TSMC, Nvidia, and AMD, participate in the organization.

Initially, the industry strictly limited the increase in HBM thickness. If HBMs grew indefinitely, it would be difficult to match the thickness of system semiconductors (such as GPUs) horizontally integrated next to them. Furthermore, if the thickness gap between DRAMs is too large, the data transmission path becomes longer, leading to a decrease in performance and efficiency.

Therefore, memory companies have been experimenting with various technologies to reduce HBM thickness. Typical examples include thinning processes (by grinding the back of the DRAM core chip) and bonding technologies (reducing the gaps between DRAMs).

However, there are two main reasons why the semiconductor industry is actively discussing reducing the thickness of next-generation HBMs.

First, the next-generation HBM adopts a 20-layer stacked structure. While current mature thinning and bonding technologies can reduce the gaps between DRAM chips, they have limitations in further thinning HBM.

Analysis indicates that the new packaging process introduced by TSMC (a major wafer foundry) has also had an impact. Currently, TSMC almost monopolizes the 2.5D process (CoWoS), which packages HBM and GPU into a single AI accelerator. 2.5D technology improves packaging performance by inserting a wide interposer between the chip and the substrate.

Industry insiders believe this discussion will slow the adoption of new bonding processes, such as hybrid bonding. Bonding is the process of connecting individual DRAM chips within an HBM, and thermoforming (TC) bonding, utilizing thermal compression, is currently the mainstream method.

Hybrid bonding technology is a technique that directly bonds copper wires between the chip and the wafer. Because there is no need to create bumps between the DRAMs, the gaps between them are almost zero. This is a significant advantage for reducing the overall thickness of HBM packages.

However, hybrid bonding technology is extremely difficult to implement. To achieve seamless bonding between chips, all tiny contaminants on the chip surface must be removed. This requires chemical mechanical polishing (CMP) to perfectly smooth the chip surface. Furthermore, high-precision alignment is needed to ensure accurate mating of each copper pad. At the same time, bonding up to 20 chips significantly reduces yield.

Therefore, major memory manufacturers have been continuously developing hybrid bonding technology, but it has not yet been widely applied to HBM manufacturing processes. Even Samsung Electronics, the most active developer of hybrid bonding technology, is expected to only partially apply it in its 16-layer HBM4E products at the earliest.

In this context, if the thickness standard for next-generation HBMs is relaxed, memory companies may continue to mass-produce HBMs using TC bonding machines.

An industry insider stated, "There's a view in the industry that reducing the HBM thickness by 50 micrometers or more would allow for 20-layer stacked HBMs." He added, "Even with the introduction of hybrid bonding technology, existing equipment cannot be completely replaced, and the investment cost is enormous, so I understand that memory companies tend to reduce the thickness of next-generation HBMs."

Source: Compiled from zdnet

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