Recently, startup NEO Semiconductor has once again announced a new technology that is expected to completely change the status quo of DRAM memory: two new 3D X-DRAM unit designs - 1T1C and 3T0C. According to reports, these two types of designs will be put into concept verification test chips in 2026, and based on the company's existing 3D X-DRAM technology, a single module of the new unit can accommodate 512 Gb (64 GB); this is 10 times more than any module currently on the market. NEO's test simulations measured a read/write speed of 10 nanoseconds and a retention time of more than 9 minutes, both of which are also at the forefront of current DRAM capabilities.

NEO pointed out that the reason for launching these solutions is that the company has seen the bottleneck of DRAM. According to them, DRAM scaling has encountered a critical bottleneck due to the challenge of reducing the size of capacitors below the 10nm technology node. Although it is extremely complex to develop a viable DRAM 3D process, there is still an urgent need for monolithic 3D DRAM arrays. This is why they launched new products and technologies.

NEO pointed out that the newly launched 3D X-DRAM 1T1C and 3T0C are a transformative solution designed to provide unprecedented density, power efficiency and scalability for the most demanding data applications.

A complete explanation about 1T1C and 3T0C

Specifically, the new 1T1C cell integrates a capacitor and a transistor. It uses a 3D NAND-like structure to reduce manufacturing costs while utilizing an IGZO (indium gallium zinc oxide) channel to enhance data retention.

Figure 1

The new 1T1C design is shown in Figure 1. Figure 2 removes the top wordline layer to reveal the internal structure of the cell. The cell cleverly integrates a transistor and a capacitor into a compact cell structure. The transistor channel is made of a thin oxide semiconductor layer, such as IGZO (Indium Gallium Zinc Oxide). IGZO is known for its extremely low off current, which can extend the storage time of the cell. Alternatively, the cell can use silicon or polysilicon as the channel material.

Figure 2

The IGZO layer is coupled to a metal wordline layer that acts as the gate of the transistor. The drain of the IGZO layer is connected to a vertical bitline made of a material. A thin high-k dielectric layer, acting as a capacitor, is located along the cylindrical sidewall on the source side of the transistor, between the IGZO channel and the capacitor plate layer. This capacitor plate is biased with VDD, which allows the N-type IGZO layer to effectively store electrons.

The capacitance value is determined by the cell size. For example, if the bitline diameter is 60nm, the channel length is 45nm, the cell height is 50nm, and the FfO2 dielectric layer is 5nm, the capacitance value is about 0.7fF. Assuming an IGZO off current of 3x10⁻19A and defining the data retention criterion as a capacitor voltage drop of 0.1V, this configuration can achieve a long retention time of more than 450 seconds.

A key factor for 1T1C DRAM is the ratio of capacitance to parasitic bitline capacitance, which must exceed 10% to ensure adequate 100mV sensing voltage during read operations. Simulation results show that this ratio exceeds 10% for 3D arrays up to 128 layers, ensuring reliable sensing voltage. For arrays with more than 128 layers, the capacitance can be enhanced by using taller capacitor walls, thinner dielectric layers, or higher-k materials.

Figure 3 shows another cell structure that adds additional spacers between the vertical bitline and wordline layers to reduce parasitic bitline capacitance. These isolation layers, which can be made of low-k dielectric materials such as silicon dioxide (SiO₂), play a key role in enabling scalability. Simulation results show that adding isolation layers with a thickness of 5 nanometers can stack cells with more than 512 layers.

Figure 3

Figure 4 shows a variation of the 1T1C design, where a conductor plate is connected to the source side of the IGZO channel, serving as a capacitor electrode for electron storage. The capacitor structure consists of a conductor plate, a gate dielectric layer, and a wordline layer, and its capacitance is determined by the area of the conductor plate.

Figure 4

Figure 5 shows another variation of the 1T1C design, similar to Figure 64, but with the insulator between the vertical bitline and the IGZO layer eliminated. This modification not only reduces the cell height, but also enables the IGZO channel to couple through both upper and lower wordline layers, thereby enhancing channel control. Note that in addition to these variations, the 3D X-DRAM family includes many other proprietary cell structures.

Figure 5

As for the 3T0C unit, three transistors with IGZO channels are integrated: a write transistor, a read transistor, and a storage transistor. Among them, the storage transistor retains data by storing electrons in its gate, thereby realizing current sensing. In NEO's view, this design is not only suitable for DRAM applications, but also for emerging memory computing and AI applications. As shown in Figure 6, this innovative unit contains two layers of IGZO layers to enhance performance. The first IGZO layer is coupled with the word line layer to form a first channel. Its source is connected to the metal gate. The word line can activate the first channel to store electrons in the metal gate.

Figure 6

When the stored data is 1 (VDD), the metal gate activates the second channel formed by the second layer of IGZO, allowing current to flow between the bit line and the source line. When the stored data is 0 (0V), the metal gate disables the second channel, preventing current from flowing. The read word line activates the third channel, enabling a read operation. Because the 3T0C cell relies on current sensing, it is particularly suitable for in-memory computing and artificial intelligence (AI) applications, where high-speed data processing and efficient power management are critical.

It is summarized that the main features and benefits of the newly launched DRAM technology include:

Unparalleled retention time and efficiency 

- mainly due to IGZO channel technology, 1T1C and 3T0C unit simulations show retention time of up to 450 seconds, greatly reducing refresh power; 

Verified by simulation 

- TCAD (Technical Computer-Aided Design) simulation confirmed fast read/write speeds of 10 nanoseconds and retention time of more than 450 seconds; 

Manufacturing-friendly

- using improved 3D NAND process, only minor changes are required to achieve full scalability and rapid integration into existing DRAM production lines; 

Ultra-high bandwidth 

- using a unique array architecture for hybrid binding, significantly improving memory bandwidth while reducing power consumption; 

High performance for advanced workloads 

- designed for artificial intelligence, edge computing and memory processing, with reliable high-speed access and reduced energy consumption;

3D X-DRAM, three variants

According to NEO, 3D X-DRAM is a disruptive technology based on an innovative capacitor-free floating cell (FPC). It uses existing NAND processes to manufacture 3D NAND-like arrays, so it can be easily scaled and cost-effective compared to other 3D DRAM solutions under development.

In addition, these designs do not require TSV (through silicon vias) and support the use of hybrid bonding technology, which can increase bandwidth by 16 times while significantly reducing power consumption and heat generation, making it a transformative innovation for AI applications.

Figure 7

The 3D array architecture of the 3D X-DRAM family is shown in Figure 7. The array is divided into multiple sectors by vertical slits. Multiple wordline layers within each sector are connected to the decoding circuitry through a stair-like structure located on both sides of the array.

This 3D array architecture has been the industry standard for many years, enabling the production of 3D NAND flash memory with more than 300 layers. Building on this success, 3D X-DRAM innovates with a similar array architecture, but with a smaller sector size. This design is able to meet high-performance needs and create high-speed, high-density DRAM solutions.

The 3D X-DRAM cell can be manufactured using a similar process to 3D NAND, with only a few modifications to accommodate the formation of IGZO and capacitors. 

In their view, the process has the following advantages:

Bitline holes require only a single mask, ensuring that all process steps are fully self-aligned. This eliminates the problem of misalignment between masks, which is particularly important for 3D arrays. As a result, the design significantly improves process yield and enables stacking of more than 300 layers. Unlike solutions that rely on a layer-by-layer approach, it can process cells in all layers simultaneously. This significantly reduces manufacturing costs. The process leverages mature 3D NAND technology, ensuring faster development cycles and higher scalability.

Figure 9

Figure 9 outlines the additional process steps to form the extra spacer layer in the cell structure shown in Figure 3:

1. After forming the vertical bitline hole, wet etch to recess the sacrificial layer. 2. Deposit an insulator to fill the recess. 3. Remove the insulator from the sidewalls of the bitline hole. Leave the remaining insulator in the recess to form the spacer layer. Then, follow process steps 2-6 in Figure 12 to complete the cell structure shown in Figure 5.

Initially, they introduced a 3D X-DRAM 1T0C design built on floating body cell (FBC) technology.

Figure 10 shows the original 3D X-DRAM, now called 3D X-DRAM 1T0C (single transistor, zero capacitance). The cell uses a floating body to store electrical holes that represent data. The electrical holes in the floating body can adjust the threshold voltage of the cell and enable current sensing during read operations, making it well suited for DRAM and in-memory computing (IMC). Currently, proof-of-concept test chips are under development.

Figure 10

Now, with the addition of 1T1C and 3T0C solutions, 3D X-DRAM has evolved into a broader family that together delivers exceptional capacity and bandwidth for modern and emerging applications.

In other words, today, the 3D X-DRAM technology platform currently includes three 3D X-DRAM variants:

1T1C (One Transistor, One Capacitor) 

– A core solution for high-density DRAM, fully compatible with mainstream DRAM and HBM roadmaps. 

3T0C (Three Transistors, Zero Capacitor) 

– Optimized for current sensing operation, ideal for AI and in-memory computing. 

1T0C (One Transistor, Zero Capacitor) 

– A floating cell structure suitable for high-density DRAM, in-memory computing, hybrid memory and logic architectures.

"With the introduction of our 1T1C and 3T0C 3D X-DRAM, we are redefining what's possible in memory technology," said Andy Hsu, founder and CEO of NEO Semiconductor. "This innovation breaks through the scaling limitations of today's DRAM."

Source: Semiconductor Industry Observer

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