The semiconductor industry is at a turning point in logic technology, with major foundries expected to showcase their 2-nanometer process technologies using gate-all-around (GAA) field-effect transistors (FETs). 

The three major players—Intel, Samsung Foundry, and TSMC—all plan to bring their 2-nanometer processes to market in 2026, named Intel 18A, Samsung SF2, and TSMC N2, respectively. The rollout of these technologies will redefine the competitive landscape in high-performance computing (HPC), artificial intelligence (AI) acceleration, and advanced mobile platforms.

The first chips to use the 2nm process will be PC and mobile SoCs, not (as many might assume) AI accelerators or HPC devices. The majority of the AI server market still relies on advanced 3nm or even 4nm processes. AMD's Venice EPYC processor is expected to be the first HPC chip to use TSMC's N2 process, with an anticipated release in 2026.

A battle between 3.5 giants

The race towards 2nm is currently a battleground primarily between Intel, Samsung, and TSMC. Additionally, Japan's Rapidus is also eyeing the market, which we can consider a 0.5 giant.

First, let's look at Intel. In February of this year, Intel was the first to market with its self-developed PC SoC chip, Panther Lake. The early deployment of the 18A chip doesn't necessarily indicate Intel's broad leadership in the foundry field, but rather demonstrates its ability to integrate advanced transistor and power delivery innovations into shipped products on time.

This achievement is both strategically significant and reflects Intel's internal strength. Intel's ability to advance its chip design reflects improved process execution capabilities. Previously, Intel's collaborations with fabless companies were limited to Microsoft—its important flagship customer—and only for small-volume products. Since the successful launch of Panther Lake, Intel has gained support from other customers, including Apple, which is undoubtedly important proof.

Intel has made two significant technological leaps in its 2nm process: GAA transistors and early adoption of back-side power supply (BSP) through PowerVia. While BSPs offer long-term advantages in power integrity and scalability, they also represent an architectural departure from traditional design approaches. Adopting BSPs requires significant design re-architecting, limiting the ability of customers accustomed to front-side power supply to immediately migrate to new systems.

In contrast, competitor foundries are expected to delay BSP implementation until later this decade, with broader industry adoption projected around 2027. This timing misalignment makes Intel's early BSP deployment both an advantage and a disadvantage: it facilitates early learning and internal optimization but raises the barrier to entry for external customers seeking near-term design migrations.

Next, consider Samsung, which is gaining credibility through yield recovery.

Samsung has now launched its Exynos 2600 smartphone SoC using its SF2 process. SF2 is not a technological leap for Samsung, as it already employed GAA architecture in its 3nm process. However, its early GAA processes reportedly had lower yields. While the SF2 architecture isn't drastically different from its predecessor compared to competitors, Samsung appears to have taken steps to address yield issues. This is evident in the re-adoption of Exynos chips in most of its Galaxy smartphones; the previous generation of Galaxy phones primarily relied on Qualcomm SoCs, indicating Samsung's ongoing efforts to improve yield to support its own products, not to mention external customers. The significance of Samsung's SF2 process lies more in the commercial than the technical aspects.

Looking at TSMC, they are consolidating their leadership through large-scale execution.

Everyone is eagerly awaiting TSMC's N2 process technology. This technology is likely to be used in Apple's iPhones before the end of the year. This will be TSMC's first application of GAA technology. Like Samsung, TSMC will not use BSP technology in this generation of products. TSMC's reputation is built on its ability to consistently deliver high-volume products on time.

While we expect this advantage to continue, it's worth noting that its most important customer, Apple, has also partnered with Intel. We believe this is unrelated to any concerns Apple may have about TSMC's continued supply capacity, and we expect Apple to continue to rely heavily on TSMC's capacity. More precisely, it's a result of "capacity constraints," excessively long lead times for advanced manufacturing processes, and geopolitical factors, as the current US administration is pushing for manufacturing to return to the US.

Now let's look at Rapidus, an emerging competitor

In 2027, another new foundry, Rapidus, will enter the artificial intelligence (AI) and high-performance computing (HPC) markets with its 2HP process technology. Its HPC business development plans are likely to be very similar to other major players. However, Rapidus may lack the experience in manufacturing processes compared to other companies. Whether Rapidus can achieve competitive yields and large-scale ecosystem support remains to be seen, but its emergence reflects the growing geopolitical and supply chain pressures driving diversification in advanced semiconductor manufacturing.

What determines the success of 2nm?

The differences between these approaches are becoming increasingly clear. Intel prioritizes architectural innovation through BSP integration; Samsung focuses on restoring manufacturing confidence after early GAA yield challenges; and TSMC continues to emphasize execution stability and ecosystem scale. Meanwhile, new players like Rapidus are emerging. As a result, the competitive landscape depends not only on transistor density but also on manufacturability, customer migration paths, and supply chain resilience.

More importantly, designing, developing, and manufacturing chips at 2nm and below requires a completely new set of business and technological trade-offs, with each step, from architectural conception to manufacturing yield, having a greater impact.

At such small dimensions, the primary goal of shrinking device features is to achieve several times the performance per watt, but this is not as simple as integrating more transistors on a silicon wafer. At such dimensions, deviations of a few atoms, or nanometer-scale voids or burrs in signal paths, can affect performance. With wires and metal layers becoming so thin, any anomaly can lead to unexpected thermal gradients and thermal migration, reducing reliability and shortening device lifespan. 

Furthermore, materials such as photoresists require extremely high purity, with impurity levels measured in parts per trillion. Complexity is exploding at every level and can have ripple effects in unexpected places. Multi-chip components can contain hundreds of billions or even trillions of transistors, various types of memory, and multi-layer/multi-chip wiring and power supply schemes. Managing all these components, both locally and globally, requires navigating multiple areas of expertise that cross traditional barriers, and almost every aspect requires multiple iterations.

From an economic perspective, almost all cutting-edge chip designs are vendor-specific or workload-specific. Well-funded companies can afford these expensive, advanced node chips, and they want chips that can be customized for specific data types and operating conditions, and they want to leverage this customization across multiple generations of derivative chips. At the same time, foundries need to be able to extend their investments beyond a single customer. The approach to meeting both needs is to use a general-purpose metal layer at the bottom of the chip stack (which typically requires very expensive tools and equipment to develop), while adding more customized elements on top of the metal stack.

Almost all of these cutting-edge chips are heterogeneous. While some logic circuitry uses 2-nanometer or 18-angstrom processes, most designs also use chips developed using older processes for packaging. Hybrid manufacturing processes are not new, but the scale and potential impact of these combinations are becoming increasingly challenging. 

Large systems companies like Google, Tesla, Microsoft, and Meta are constantly pursuing higher performance, requiring areas larger than a single photomask can provide. At least until now, the solution has been to partition different functions into chipsets and connect them using an interposer, resulting in a logic density per system far greater than that of a single photomask-sized SoC. However, as the number of chipsets increases, this approach easily transforms from a problem into an insurmountable one.

The biggest advantage of scaling to the most advanced process nodes lies in reducing power consumption per square millimeter. In the past, scaling processes simply to increase transistor count—the standard approach to performance improvements before the FinFET era—has yielded very limited performance gains over the last five process nodes.

Results have varied across foundries, but performance gains per node have rarely exceeded 20% (sometimes even in the single digits), often at the expense of power consumption. This, in turn, has led to a proliferation of 2.5D architectures (within AI data centers), consisting of general-purpose processors and highly specialized accelerators connected by large silicon interposers.

CPUs, GPUs, DSPs, MCUs, and FPGAs are general-purpose processors, while NPUs and TPUs are used to process specific data types. New hybrid processors are also emerging, such as Arm's new AGI CPUs and some neuromorphic processors. However, achieving significant performance gains requires combining multiple types of processors, whether integrated on a single chip, interconnected within a package, mounted on a circuit board, or in a rack. Moreover, regardless of the approach, extensive heat dissipation and device monitoring are required to ensure unobstructed data paths between the processor and memory.

Furthermore, shrinking process dimensions to below 3nm leads to increased gate leakage current, resulting in severe leakage current issues in FinFETs. This, in turn, increases heat density, exacerbating the heat dissipation problem. Currently, the solution is to use gate-around field-effect transistors (also known as nanosheets), but chipmakers are developing complementary field-effect transistor processes, expected to be implemented within the next few angstrom nodes.

In conclusion, the criteria for measuring the transition to 2nm processes will not be solely based on transistor density. Yield stability, ecosystem compatibility, power supply architecture, and manufacturing scale will determine which foundries will succeed in the 2nm era. As the industry transitions from the FinFET era to the GAA era, the competition is no longer about who reaches the new process node first, but about who can reliably produce the required devices on a large scale.

Source: Semiconductor Industry Observer

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