A collaborative team has manufactured the first monolithic 3D chip at a U.S. wafer foundry, achieving the densest 3D chip wiring and orders of magnitude speed improvement.

Engineers from Stanford University, Carnegie Mellon University, the University of Pennsylvania, and MIT, in collaboration with Skywater, the largest pure-play semiconductor foundry in the U.S., have developed a new type of multi-layered computer chip whose architecture could help usher in a new era of AI hardware and domestic semiconductor innovation.

Unlike most current flat 2D chips, the key ultra-thin components of this new prototype chip extend upwards like the floors of a skyscraper, with vertical wiring resembling numerous high-speed elevators, enabling fast, massive data transmission. Its record-breaking vertical interconnect density and meticulously interwoven storage and computing units help the chip overcome long-standing bottlenecks hindering improvements in flat designs. In hardware testing and simulations, this new 3D chip outperforms 2D chips by approximately an order of magnitude.

While experimental 3D chips have been manufactured in academic labs before, this is the first time such a chip has demonstrated a significant performance improvement and achieved mass production at a commercial foundry. "This ushers in a new era of chip manufacturing and innovation," said Subhasish Mitra, William E. Ayr Professor of Electrical Engineering and Professor of Computer Science at Stanford University. He is the lead author of a new paper describing the chip, presented at the 71st IEEE International Electron Devices Meeting (IEDM 2025) in San Francisco, December 6-10. "It is breakthroughs like these that allow us to achieve the 1,000-fold hardware performance improvement needed for future AI systems."

Challenges of planar chips

Modern AI models like ChatGPT and Claude must transfer massive amounts of data back and forth between memory for storing information and computing units for processing it.

On traditional two-dimensional chips, components are arranged on a flat surface with limited and dispersed memory, forcing data to travel along several long and congested paths. Because computing units operate much faster than data transfer, and the chip cannot store enough memory nearby, the system eventually becomes constantly waiting for information. Engineers call this bottleneck the "memory wall"—the critical point where processing speed exceeds the chip's data transfer capacity.

For decades, chip manufacturers have been trying to address the memory bottleneck by shrinking the size of transistors (tiny switches on a chip that perform computations and store data) and integrating more transistors onto each chip. But this strategy is also approaching its physical limits, which researchers call the "miniaturization bottleneck."

This new type of chip overcomes these limitations by extending vertically upwards. "By vertically integrating memory and computing, we can move more information much faster, much like an elevator in a high-rise building allows many residents to move between floors simultaneously," said Tathagata Srimani, assistant professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University and senior author of the paper. He initially began this research as a postdoctoral researcher under Mitra's guidance.

"Memory bottlenecks and miniaturization bottlenecks form a deadly combination," said Robert M. Radway, assistant professor in the Department of Electrical and Systems Engineering at the University of Pennsylvania and co-author of the study. "We tackled it head-on, tightly integrating memory and logic, and then building upwards at extremely high density. It's like Manhattan in the computing world—we can fit more people in a smaller space."

How are new 3D chips manufactured?

To date, most attempts at 3D chip development have relied on stacking individual chips. While feasible, this approach results in coarse, sparse interlayer connections and is prone to bottlenecks.

Instead of the traditional method of fabricating multiple chips and then fusing them, the research team employed a sequential process, directly stacking each layer on top of the previous one. This monolithic process uses sufficiently low temperatures to avoid damaging the underlying circuitry, allowing researchers to stack components more tightly and achieve higher-density interconnects.

More importantly, the entire process was completed at a domestic commercial silicon wafer fab. "Translating cutting-edge academic concepts into products that can be manufactured in a commercial wafer fab is a huge challenge," said Mark Nelson, co-author of the paper and vice president of technology development operations at SkyWater Technology. "This demonstrates that these advanced architectures are not only feasible in the lab but can also be mass-produced domestically, which is exactly what the U.S. needs to maintain its leadership in semiconductor innovation."

Chip performance and potential

Early hardware testing indicates that the prototype chip already outperforms comparable 2D chips by approximately four times. Simulations of higher, future versions (with more stacked memory and compute layers) show even more significant performance improvements. The multi-layered design achieved up to 12x performance gains on real-world AI workloads, including those derived from Meta's open-source LLaMA model.

Most notably, researchers say this design paves a viable path to increasing the Energy Delay Product (EDP) by 100 to 1000 times, a key metric for balancing speed and energy efficiency. By significantly reducing data transmission distances and adding more vertical paths, the chip can simultaneously achieve higher throughput and lower power consumption per operation, something long considered unattainable for traditional flat architectures.

Researchers emphasize that the long-term implications of this research extend far beyond performance. They state that by demonstrating that a monolithic 3D chip can be manufactured domestically in the United States, this work lays the groundwork for a new era of domestic hardware innovation, enabling the U.S. to design and manufacture state-of-the-art chips.

Just as the integrated circuit revolution of the 1980s was driven by students learning chip design and manufacturing in U.S. labs, researchers say the shift to vertical monolithic 3D integration will require a new generation of engineers proficient in these technologies. Through collaboration and funding, students and researchers are being trained to drive semiconductor innovation in the United States.

"These kinds of breakthroughs are certainly about performance, but they’re also about capability," said Hongsheng Huang, Willard R. Bell and Inez Kerr Bell Professor of Engineering at Stanford University and principal investigator at the Northwest Artificial Intelligence Center. "If we can build advanced 3D chips, we can innovate faster, respond faster, and shape the future of AI hardware."

Source: Compiled from techxplore

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