In 2024, imec introduced CMOS 2.0 as a new scaling paradigm to address the growing computing demands driven by diverse applications. In CMOS 2.0, systems-on-chip (SoCs) are divided into distinct functional layers (or tiers) guided by system technology co-optimization (STCO). Each functional layer is built using the technology that best matches the functional constraints.

Advanced 3D interconnect technology reconnects the heterogeneous layers of the SoC. This is reminiscent of an evolution already in commercial computing products: imagine 3D stacking SRAM chips on a processor. However, the hallmark of the CMOS 2.0 approach is the introduction of heterogeneity within the SoC. Depending on application requirements, CMOS 2.0 even envisions splitting the logic portion of the SoC into a high-drive logic layer (optimized for bandwidth and performance) and a high-density logic layer (optimized for logic density and performance/watt). The high-density layer can be manufactured using the most advanced technologies, including the largest transistor architectures.

Figure 1: Example of possible SoC partitioning in the CMOS 2.0 era

Another key feature is the backside power delivery network (BSPDN): some active devices are powered from the backside of the wafer, rather than the traditional frontside. This enables extremely high back-end-of-line (BEOL) pitch patterning on the frontside of the wafer, unconstrained by supply voltage drop.

Essentially, in this approach, the device wafer is modified to become a very thin front-end-of-line (FEOL) active device layer, with a dense stack of back-end-of-line (BEOL) signal routing layers on one side (the former "frontside") and power and external I/O connections on the other side (the former "backside," but now the new frontside). Multiple such thin device layers can be stacked, each with dense interconnects. Each layer can integrate different types of devices, such as logic, memory, electrostatic discharge (ESD) protection, voltage regulation circuits, and more. We call this dense stacking of 3D device layers CMOS 2.0.

This system-scaling approach will enable chip design and manufacturing to move away from the general-purpose CMOS technology platform, which has served the semiconductor industry for decades but has struggled to fully meet the growing and diverse demands of computing. This approach helps address computing system scaling bottlenecks, bringing value to every player in the semiconductor ecosystem, including system companies and fabless companies.

3D Interconnect and Backside Technology: The Foundation of CMOS 2.0

CMOS 2.0 relies on all previous semiconductor innovations, including logic device scaling, memory density scaling, advanced lithography, 3D integration, and back-side surface-dispersed nanostructured (BSPDN) technology. However, recent breakthroughs in 3D interconnect and backside processing technologies are making this concept a reality. For example, wafer-to-wafer hybrid bonding is beginning to offer submicron interconnect pitch connections. This allows for interconnect density matching that of the last metal layer of the back-end (BEOL)—a key enabler for stacking logic-on-logic or memory-on-logic layers via hybrid bonding. With direct access to transistor terminals, backside power delivery technology is expected to advance to even finer granularity. While initially targeted at power connections, this capability also opens the possibility of migrating fine-grained signal connections to the backside. This allows any device technology layer to be suspended between two independent interconnect stacks.

The combination of fine-pitch bonding and fine-grained backside processing (Figure 2) is fundamental to realizing the CMOS 2.0 vision illustrated in Figure 1.

Figure 2 – Schematic diagram of high-density face-to-face hybrid bonding and backside high-density connection networks (shown in 2025 VLSI [4]). (PADT = top pad; PADB = bottom pad; TDV = through-dielectric via.)

At the 2025 VLSI Conference, imec reported on advances in two 3D integration technologies: wafer-to-wafer hybrid bonding and backside vias, which are fundamental to achieving CMOS 2.0.[4] These technologies lay the foundation for designing new system architectures around the CMOS 2.0 vision guided by STCO, in which backside via networks (BSPDNs) will play a central role. Also at the 2025 VLSI Conference, imec researchers highlighted the power-performance-area-cost (PPAC) advantages that such BSPDNs can bring to advanced system architectures.[5]

Wafer-to-wafer hybrid bonding toward 250nm pitch: A roadmap view

Over the years, various 3D interconnect technologies have been developed, covering a wide range of interconnect pitches and addressing diverse application requirements. Of these technologies, wafer-to-wafer hybrid bonding is best suited to deliver the 3D interconnect pitch and density required for stacking logic layers on memory/logic in the CMOS 2.0 environment. The copper pads of wafer-to-wafer bonding provide short, direct, low-resistance connections from one layer to another. 

At reduced pitches, wafer-level connections can deliver high bandwidth density and reduce power per bit during signal transmission.

Figure 3 – Imec's 3D interconnect technology scaling roadmap shows the different technologies required for different interconnect densities. (BGA = ball grid array; CSP = chip scale package; W2W = wafer-to-wafer; Mx, My, and MR represent the BEOL interconnect hierarchy).

Classic wafer-to-wafer hybrid bonding process flow

The classic hybrid bonding process (Figure 4) begins with two fully processed 300mm wafers, including the complete front-end-of-line (FEOL) and back-end (BEOL) processes (see also Figure 2). The first part of the process resembles an on-wafer BEOL damascene process, etching a small cavity in the bonding dielectric—primarily using SiO2. The cavity is then filled with a barrier metal, seed, and copper. This is followed by a chemical mechanical polishing (CMP) step optimized for high wafer-to-wafer uniformity, resulting in an extremely flat dielectric surface while achieving a controlled recess of a few nanometers for the copper pads. After precise alignment, the actual bonding of the two wafers occurs at room temperature by contacting the wafers at their centers. 

The adhesive properties of the polished wafer surfaces result in a strong attractive force between the wafers, generating a bonding wave that closes the gap between the wafers from center to edge. After this room-temperature bonding step, the wafers are annealed at a higher temperature to achieve permanent dielectric-to-dielectric and copper-to-copper bonds.

Figure 4 - Classic wafer-to-wafer hybrid bonding process flow

Reliable 400nm pitch wafer-to-wafer connectivity

At IEDM 2023, imec demonstrated reliable 400nm pitch wafer-to-wafer connections with high yield, a significant improvement over the 1µm pitch connections used in industrial wafer-to-wafer bonding processes [6]. 

This leap in interconnect pitch is due to several process improvements, including enhanced control over the wafer surface topology and the use of SiCN as a bonding dielectric. SiCN has been found to provide superior bond strength and scalability compared to traditional SiO2.

Driving the hybrid wafer-to-wafer bonding roadmap toward 200nm pitch

As we move deeper into the system layer—ultimately splitting the logic into dedicated logic layers—bond pitches below 400nm are required, pushing the wafer-to-wafer hybrid bonding roadmap toward 200nm pitches. However, as the pitch continues to shrink, the requirements for the bond overlay between the two copper pads increase. Typically, the bonding process's overlay accuracy is equivalent to one-quarter of the pitch, and for a 200nm pitch, overlay accuracy can be as low as 50nm. Achieving such high accuracy at the 300mm wafer scale is the greatest challenge in achieving higher interconnect density today.

To further advance this roadmap, imec researchers are working to gain a deeper understanding of the bonding process and the factors that influence high overlay accuracy. It is well known that during the bonding process, the two wafers can easily deform and distort, hindering accurate overlay between the copper pads. The team's simulations revealed that the bonding wave generated when the two wafers are bonded does not propagate uniformly—a phenomenon believed to be the root cause of wafer deformation. These findings are enabling the development of models that can predict the extent of wafer deformation and ultimately adjust the bonding process. This knowledge can also help improve overlay accuracy in another way: designers can adjust the copper pad position according to the pattern design before actual wafer bonding. These pre-bonding lithography corrections enable imec to achieve wafer-to-wafer hybrid bonding at a 300nm pitch using today's most advanced bonder tools, with an overlay error of less than 25nm for 95% of the chips.

At the VLSI 2025 conference, imec researchers demonstrated the feasibility of further extending the wafer-to-wafer hybrid bonding roadmap to an unprecedented 250nm pitch. However, achieving the required overlay accuracy on 300mm wafers at industry-relevant yields requires next-generation bonding equipment. Imec will continue to collaborate with its ecosystem of tool suppliers to advance towards this ambitious goal.

Figure 5 – TEM of a daisy chain (bonding top (PADT) and bottom (PADB) pads of varying sizes) on a 250nm hexagonal pad grid

Figure 6 – Electrical yield of a hybrid bonded daisy chain versus pad pitch for unequal pad sizes

Using nano-silicon vias to connect the metal on the front and back of the layer

In CMOS 2.0 implementations, the layer stacking will be much more complex than today's hybrid bonding in the industry. Instead of two layers, the stack will consist of multiple layers. Most layers will have metal lines on both sides (front and back), with an active layer (such as memory or logic) in the middle. Some of the backside metal lines can be used to power active devices as part of a broader BSPDN.

Front-to-back connectivity through direct backside contacts and nano-silicon vias

Following this vision, today's hierarchical structures feature connectivity on both sides, seamlessly connecting the front and backside metals. This front-to-back connectivity can be achieved through silicon vias (TSVs) down to the logic or memory cell level. As system hierarchies grow, other front-to-back connections, including direct backside contacts, are required at finer interconnect pitches. This connection scheme can be used to connect the source/drain contact areas of advanced logic devices directly to the backside metal and is emerging as an emerging technology in the logic roadmaps of leading foundries.

Advances in front-to-back connectivity technology must keep pace with advances in the wafer-to-wafer hybrid bonding roadmap to provide close-pitch connectivity on both sides of the wafer in a balanced manner (see Figure 2). However, combining all these technologies presents challenges. The wafer-to-wafer bonding step requires increasing post-processing, including wafer thinning (to support TSV fabrication) and backside metal patterning. In this latter step, minimizing backside lithography distortion is crucial to ensure close overlap between the backside metal lines and the TSVs or source/drain contacts.

Backside dielectric via with a bottom diameter of 20nm

At the VLSI 2025 conference, imec showcased progress in its nano-through-silicon-via (nTSV) roadmap, demonstrating backside vias with diameters as small as 20nm and a pitch of 120nm. 

Vias of this size have the advantage of occupying as little standard cell area as possible, but their fabrication requires extreme wafer thinning to ensure a manageable aspect ratio.

Figure 7 – TEM of front-to-back connection using barrier-free Mo-filled TDV with a bottom diameter of 20nm

Imec's roadmap offers multiple options for fabricating nTSVs, including via-first, via-in-the-middle, and via-last integration. Furthermore, the via bottom can be rounded or slit-shaped, sacrificing area for better overlay tolerance. In the 2025 VLSI demonstration, the vias were fabricated using a via-first approach, meaning they were patterned within the shallow trench isolation (STI) features on the front side of the wafer before wafer thinning. The resulting through-dielectric vias (TDVs, so called because they penetrate the STI dielectric) were filled with molybdenum (Mo). Mo can be fabricated without a barrier layer and offers lower resistance than traditional Cu or W metals, resulting in both area and performance benefits.

Joining front and back sides with high registration accuracy

The layout of a typical test structure shows a 15nm overlay margin between the 55nm-wide backside metal line and the 20nm-wide Mo TDV circular bottom. 

This overlay specification is achieved by using high-order correction at each exposure during the backside metal lithography step to compensate for grid distortion caused by the previous wafer bonding and thinning steps.

Figure 8 – Layout showing 15nm overlay margin between the bottom of the TDV and the 55nm wide backside metal. (TEM1 represents the TEM cut used in Figure 7.)

In all previously discussed connection schemes, achieving high total overlay accuracy in hybrid bonding and minimizing backside lithography distortion are key goals, which depend both on the bonding process and the capabilities of the next-generation bonding equipment.

Performance and area advantages of BSPDN in always-on and switched domain designs

BSPDN is another key feature of the future CMOS 2.0 architecture. With BSPDN, the entire power distribution network is moved to the back side of the wafer, which allows for larger interconnects and lower resistance. As a result, BSPDN can significantly reduce the supply voltage (or IR) drop. This helps designers maintain a 10% margin to account for unnecessary power losses between the voltage regulator and active devices. By separating the power network from the signal network, BSPDN can also alleviate BEOL congestion on the front side of the wafer, allowing for more efficient signal transmission design.

Imec first proposed the concept of BSPDN in 2019 and proposed several solutions for implementing BSPDN [8]. Some mainstream chip manufacturers have recently incorporated this technology into their logic roadmaps and plan to launch commercial products equipped with advanced processors based on BSPDN. This technology has also shown good prospects in 3D SoC implementations, and CMOS 2.0 architecture is expected to benefit from it.

BSPDN in always-on and switched-domain designs:

Performance and area improvements compared to front-end implementations

Previously, imec has demonstrated the PPAC benefits of BSPDN at the module level for high-density and high-drive logic use cases. These benefits were confirmed through a Design Technology Co-Optimization (DTCO) study for always-on use cases—architectures where power (i.e., global VDD) is continuously delivered to active devices.

At VLSI 2025, imec also demonstrated the benefits of implementing BSPDN in switch-domain designs, where blocks of standard cells are shut down for power management. Switch-domain designs are implemented by locally implementing power switches: these devices distribute power (local VDD) to transistors and can turn groups of standard cells on and off as needed. Such designs are typically used in power-constrained applications, such as mobile phones.

imec researchers compared the impact of using BSPDN in switch-domain designs with a traditional front-end PDN implementation. The study was conducted using a physical implementation of a mobile computing processor design built on 2nm technology.

Figure 9 – (a-b) Power delivery in a switch domain design, with power switches arranged in a checkerboard pattern; (c-d) Power switch layout for the front and back PDNs. (VDDEXT = normally-on power supply; VDD = switching power supply; PS = power switch.)

Compared to a front-end PDN switch domain design, the BSPDN implementation not only improves performance but also reduces area. The BSPDN significantly reduces IR drop (by 122mV). This enables the BSPDN design to use fewer power switches while still maintaining an acceptable IR drop. The reduced power switches also reduce the core area compared to the front-end PDN implementation: the total area reduction achieved with the BSPDN implementation is 22%.

Conclusion

With the advent of CMOS 2.0, a new scaling paradigm will emerge to meet the growing diversity of computing applications. It relies on stacking functional layers - each optimized using the most appropriate technology (node). Fine-grained backside processing and fine-pitch hybrid bonding are key to realizing this vision. Recent advances in wafer-to-wafer hybrid bonding, driven by SRAM partitioning, and backside technology, driven by power delivery optimization, are bringing the CMOS 2.0 concept closer to reality, providing layer-to-layer connectivity at the granularity of logic and memory standard cells. These foundational technologies will enable heterogeneity within the SoC itself - the core of the current chiplet approach - creating more options for computing system scaling.

Reference Link

https://www.imec-int.com/en/articles/path-high-density-front-and-backside-wafer-connectivity

Source: Content compiled from imec

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