As industry bandwidth demands continue to grow, PCI Express (PCIe) technology - recognized as the preferred high-bandwidth interconnect for over two decades - is poised to meet the evolving demands of the computing continuum. The PCIe 8.0 specification targets 256.0 GT/s (up to 1 TB/s bidirectionally in a x16 configuration) and is scheduled for release to members in 2028.

The PCIe 8.0 specification is expected to provide a scalable interconnect solution for emerging applications such as artificial intelligence/machine learning, high-speed networking, edge computing, and quantum computing; and support data-intensive markets such as automotive, hyperscale data centers, high-performance computing (HPC), and military/aerospace.

PCIe 8.0 Specification Feature Goals

• Delivering 256.0 GT/s raw bit rate and up to 1 TB/s bidirectional transfer rate in a x16 configuration; 

• Reviewing new connector technologies; 

• Confirming that latency and FEC targets will be achieved; 

• Ensuring that reliability targets are met; 

• Maintaining backward compatibility with previous generations of PCIe technology; 

• Developing protocol enhancements to increase bandwidth; 

• Continuing to emphasize technologies that reduce power consumption.

Al Yanes, PCI-SIG President and Chairman, said, "Following the release of the PCIe 7.0 specification this year, PCI-SIG is pleased to announce the PCIe 8.0 specification, which doubles the data rate to 256 GT/s, continuing our tradition of doubling bandwidth every three years to support next-generation applications. As AI and other applications demand ever-increasing data throughput, the need for high performance remains strong. PCIe technology will continue to provide the cost-effective, high-bandwidth, low-latency I/O interconnect needed to meet industry needs."

Reece Hayden, Principal Analyst at ABI Research, said, "As AI and other data-intensive applications continue to rapidly expand, PCIe technology will continue to see long-term demand growth due to its high bandwidth, scalability, and power efficiency. Data center networks are already preparing for the implementation of PCIe 6.0 technology and have shown strong interest in the PCIe 7.0 specification. The introduction of the PCIe 8.0 specification further ensures that the industry's future bandwidth needs will be well supported."

PCIe 8.0 The specification is designed to support emerging applications such as artificial intelligence/machine learning, high-speed networking, edge computing, and quantum computing; as well as data-intensive markets such as automotive, hyperscale data centers, high-performance computing (HPC), and military/aerospace.

UCIe Alliance launches 3.0 specification with 64 GT/s performance

The Universal Chip Interconnect (UCIe) Alliance today announced the release of the UCIe 3.0 specification, marking the next stage in the evolution of its open chiplet standard. The new specification significantly improves performance, specifically supporting data rates of 48 GT/s and 64 GT/s, while also offering incremental architectural updates to meet the industry's growing demand for high-speed, interoperable chiplet solutions. The UCIe™ Alliance is the open standard for chip-in-package interconnects.

The UCIe 3.0 specification also introduces enhancements such as runtime recalibration for improved power efficiency and extended sideband coverage to support more flexible multi-chip configurations. Additionally, additional management features, such as early firmware download and prioritized sideband packets, improve system responsiveness and reliability. The specification's optional management features give companies the flexibility to implement only the features they need, enabling a wide range of applications while allowing for design customization without unnecessary chips.

These advancements demonstrate the Alliance's commitment to driving innovation in the chiplet ecosystem by improving bandwidth density, power efficiency, and system-level manageability—key enablers of scalable, multi-chip system-in-package (SiP) designs. As a result, the 3.0 specification enables greater scalability, flexibility, and interoperability, accelerating innovation in modular semiconductor design.

"UCIe 3.0 represents a critical step forward for the chiplet industry, delivering the speed, efficiency, and manageability required to scale multi-chip designs," said Cheolmin Park, President of the UCIe Alliance and Vice President of Samsung Electro-Mechanics. "With higher data rates and enhanced manageability, next-generation UCIe technology will enable developers to build more flexible, interoperable, and high-performance SiP solutions. Together, we will build a truly open and interoperable chiplet ecosystem."

UCIe 3.0 Specification Highlights:

• Support for 48 GT/s and 64 GT/s data rates doubles the bandwidth of UCIe 2.0 (32 GT/s) to meet the needs of high-performance chiplets. 

• Runtime recalibration enhancements enable energy-efficient link adjustments during operation by reusing initialization state.

• Extended sideband channels up to 100 mm enable more flexible SiP topologies. 

• Support for continuous transfer protocols through mapping enables uninterrupted data flow in raw mode for new applications such as connections between SoCs and DSP chips. 

• Standardization of early firmware downloads using the Management Transport Protocol (MTP) simplifies initialization. Priority sideband packets enable deterministic, low-latency signaling of time-sensitive system events. 

• Fast throttling and emergency shutdown mechanisms provide immediate, system-wide notification via open-drain I/O. 

• Full backward compatibility with all previous UCIe specifications enables seamless integration and adoption.

Source: Content from Semiconductor Industry Observation

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