A new power technology for 3D integrated chips has been developed by adopting a three-dimensional stacked computing architecture consisting of processing units placed directly above a dynamic random access memory stack.

01 Background

Part covers electronic device requirements, traditional technology limitations and the new BBCube approach.

Electronic requirements

From simple home appliances like TVs to laptops and smart watches, electronic devices have transformed our daily lives. Advances in semiconductor manufacturing technology and chip packaging processes are key to the explosive growth of these electronic devices. 

However, in today's era of artificial intelligence (AI) and high-performance computing, the demand for faster and more efficient processors remains unmet.

Traditional limitations

The traditional system-in-package (SiP) approach uses solder bumps to arrange semiconductor chips on a two-dimensional (2D) plane, but its size is limited and there is an urgent need to develop new chip integration technologies.

BBCube Innovation

To this end, a research team at Science Tokyo in Japan conceived an innovative 2.5D/3D chip integration method called BBCube. In addition, they developed three key technologies to promote the practical application of BBCube.

02 Technology Development

This section focuses on the details of COW processes, adhesives and bonding technologies.

COW Process

The research team, which includes Distinguished Professor Norio Chujo, Takayuki Ohba and other scientists from the Heterogeneous and Functional Integration Division of the WOW Alliance, an integrated research center at the Tokyo Institute of Science (Science Tokyo), Japan, initially developed a face-down chip-on-wafer (COW) process to circumvent the limitations of using solder interconnects.

Explaining the precise COW process, Chujo commented: "More than 30,000 chips of different sizes were fabricated onto the waffle wafer, achieving faster bonding speeds and without any chip-off failures."

Adhesive Innovation

To achieve this precise and high-speed COW process, the researchers turned their attention to solving the thermal stability issues that may affect the multi-layer stacking of ultra-thin wafers. By carefully designing the chemical properties, they developed a new adhesive material DPAS300 that can be used in COW and wafer-to-wafer processes. 

This new adhesive consists of an organic-inorganic hybrid structure and has shown good adhesion and heat resistance in experimental studies.

Bonding Technology

Using inkjet technology and selective adhesive coating methods, they successfully bonded chips of different sizes sequentially onto a 300 mm waffle wafer, with a chip-to-chip spacing of only 10 μm and a minimum placement time of less than 10 milliseconds.

03 Results Advantages

Parts include architecture implementation, performance data, and conference presentations.

Architecture Implementation

Finally, to achieve high memory bandwidth and improve BBCube's power integrity, scientists adopted a 3D xPU-on-DRAM architecture and enhanced it with a new power distribution highway. This included embedding capacitors between the xPU and DRAM, implementing a redistribution layer on the waffle wafer, and placing through-silicon vias in the wafer channels and DRAM scribe lines.

Performance Improvement

Highlighting the advantages of 3D stacked computing architectures, Chujo said: "These innovations reduce the energy required for data transmission to one-fifth to one-twentieth of conventional systems, while also suppressing power supply noise to less than 50 mV."

Conference Presentation

Their research and results were recently presented at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), held from May 27 to May 30, 2025. (Interested friends can click the link to check it out: https://ectc.net/program/75-ECTCFinal-Web.pdf) Overall, the chip integration technology developed by researchers at Tokyo University of Science has the potential to change the next generation of computing architecture.

Reference link

https://techxplore.com/news/2025-06-3d-chip-stacking-method-traditional.html

Source: Content compiled from techxplore

View more at EASELINK