In today's digital age, chips, as the core of modern technology, have penetrated into every corner of our lives, from smartphones to artificial intelligence, from automotive electronics to IoT devices.

Chips are everywhere. However, do you know that behind these tiny but powerful chips, there is a group of unsung "heroes" - EDA tools? As a chip quality manager, I have personally experienced the entire process of chip design and I know the key role of EDA tools. The following is an in-depth analysis of the importance of EDA tools in chip design, combined with the latest industry research reports and practical experience, to present you with a comprehensive and objective perspective.

EDA tools: the cornerstone of chip design

1. Importance of EDA Tools

EDA tools are indispensable software tools in the process of integrated circuit design, manufacturing, packaging and testing. They run through every link of chip design, from conceptual design to final product manufacturing, providing strong support for chip design. According to research by University of California, San Diego Pro Andrew Kahn, the advancement of EDA technology has increased design efficiency by nearly 200 times, reducing the design cost of consumer-grade SoCs from $7.7 billion to $45 million. This data fully demonstrates the great value of EDA tools in reducing design costs and improving design efficiency.

2. Classification of EDA tools

EDA tools can be divided into front-end design tools, back-end design tools and verification tools according to their use in chip design. Front-end design tools are mainly used to implement logical functions, back-end design tools focus on physical implementation, and verification tools are used to ensure the correctness and reliability of the design.

Front End Design: From Concept to Logic

1. HDL writing tools: the "programming language" of chip design

HDL (Hardware Description Language) is the basis of chip design. It is similar to the programming language in software development and is used to describe the logical functions of the chip. Commonly used HDL languages are Verilog and VHDL. HDL writing tools are like programmers' IDEs, providing a graphical or textual design environment and supporting modular and hierarchical design. For example, VisualHDL (Summit), Renoir (Mentor), and Composer (Cadence) are all commonly used HDL writing tools.

In actual work, we ensure the readability and maintainability of HDL code through strict code review and standardized writing processes. At the same time, with the powerful functions of HDL writing tools, we can quickly locate and fix bugs and potential risks in the code.

2. Simulation tools: ensuring design is correct

Simulation verification is a crucial part of chip design. It is like unit testing in software development, which is used to verify whether the design meets the required specifications. Simulation tools can simulate the behavior of chips under various working conditions to help designers find and fix potential problems. Commonly used simulation verification tools include ModelSim (Mentor), VCS (Synopsys), and NC-Verilog (Cadence). In actual work, we use multiple rounds of simulation verification to ensure the stability and reliability of the design in different scenarios. Simulation verification not only helps us discover design defects in advance, but also provides an important reference for subsequent PV. As shown in the figure below, the NC-Verilog model skips a few parts in the middle.

In the U_drink_machine module, select the signal to be displayed in the waveform window. After selection, click the waveform button to observe the waveform.

3. Synthesis tools：Code into Circuits=

Synthesis is the process of converting HDL code into Netlists, integrating TOM (Transformation Tran+Opti+Mapping). This process is equivalent to converting "abstract Algorithm" into "logic circuit implementation". Synthesis tools need to rely on the Standard cell library of a specific process to ensure the physical feasibility of the design. For example, Design Compiler (Synopsys) is an industry standard tool in this field. It supports PPA and Speed optimization and can generate efficient Netlists according to design requirements.

DC will divide the circuit into the following processing objects during the synthesis process:

• Design: Synthesis object (module);

• Port: Design's outermost port;

• Clock: clock;

• Cell: instantiated module;

• Reference: instantiated original circuit.

In practice, we optimize the parameter settings of logic synthesis to ensure that the generated Netlist achieves the best balance between performance and power. The synthesis library must be compatible with the Fab design rules to ensure that the netlist generated by logic synthesis meets the manufacturing requirements during physical implementation.

• Standard Cell Library: Contains the physical implementation of various logic gates (such as AND, OR, NOT, etc.) and storage cells (such as FF and Latches).

• Process parameters: Define the electrical and physical characteristics of these standard cells under a specific manufacturing process.

• Optimization parameters: Used to guide the synthesis tool to balance between area, power consumption and performance.

4. STA: Ensure clock synchronization

STA is the process of checking whether the clock relationship during data transmission is reasonable. It is like an auditor, ensuring that the right signal in the chip can reach the right port at the right time. Timing analysis tools focus on constraints such as setup time and hold time to prevent the chip from being "Functionally correct but unstable".

For example, PrimeTime (Synopsys) is the de facto standard tool for timing analysis, which supports complex constraint analysis and can accurately evaluate timing.

As a quality management personnel, I am well aware of the impact of timing issues on chip stability. In actual work, we use strict timing analysis to ensure the timing stability of the design under various working conditions.

5. Formal Verification Tools: Ensure Logical Consistency

Formal verification tools are used to verify whether the functions before and after synthesis are consistent and prevent logic deformation during the synthesis process. This process is equivalent to "checking whether the source code and compiled code are semantically consistent." For example, Formality (Synopsys), LEC (Cadence), and FormalPro (Mentor) are commonly used formal verification tools. They use mathematical methods to prove the logical correctness of the design and ensure that the design still meets the original specifications after synthesis.

Compared with dynamic simulation, formal verification belongs to static verification, which does not require manual injection of stimulus. It checks the design under test through mathematical analysis.

In practice, we ensure the integrity and consistency of the design at the logical level through rigorous checks using formal verification tools.

Back End Design: From Logical to Physical

1. DFT tools: Let the chip "come with its own physical examination report"

DFT tools are used to add test structures to the design so that the functional correctness of the chip can be verified after production. DFT is a key design link that allows the chip to "come with its own physical examination report". For example, DFT Compiler (Synopsys) can insert the Scan chain, TetraMAX (Synopsys) can generate ATPG, and MBIST Architect (Mentor) focuses on memory testing.

In actual work, we use DFT tools to optimize the design to ensure that the chip can complete functional testing quickly and accurately after production.

2. PnR tools: building the "blueprint" of the chip

Place and routing tools convert gate-level netlists into physical layouts to determine the planned and linked devices. This process is like "designing the building blueprint" and "constructing the wiring" in building construction. Commonly used PnR tools include IC Compiler (Synopsys), Encounter (Cadence) and Design Planner (Mentor). These tools not only need to consider the placement of the device, but also need to optimize the routing path to ensure that the chip area, power and performance are optimized.

Floorplan (wiring) is a job that requires a lot of effort. It is said that the biggest gap between experts and novices in backend implementation is this step.

In practice, we ensure the manufacturability and reliability of the chip at the physical level by optimizing the layout and routing design.

3. CTS tool: building the "nerve center" of the chip

The clock tree synthesis (CTS) tool is used to optimize the path balancing from the clock to each register. The clock signal is like the "nerve center" of the chip, ensuring that all signals can arrive synchronously. For example, Clock Tree Compiler (Synopsys) and CT-Gen (Cadence) are commonly used CTS tools. They optimize the structure of the clock tree to ensure that the delay of the clock signal is consistent throughout the chip, thereby improving the performance and reliability of the chip.

In actual work, we optimize the design of the clock tree to ensure the stability and reliability of the chip in terms of clock signals.

4. Parasitic parameter extraction tools: evaluate signal integrity

Parasite parameter extraction is based on the physical characteristics of the layout. It extracts the parasitic effects between wires and devices to deal with the impact of signal integrity. Parasitic parameter extraction tools are used to extract capacitance, resistance and coupling effects in wires and evaluate signal integrity. These parasitic parameters will affect the transmission of signals, so they need to be accurately evaluated through extraction tools. Commonly used parasitic parameter extraction tools include Star-RCXT (Synopsys), Calibre xRC (Mentor) and Assure RCX (Cadence). These tools can generate detailed parasitic parameter reports to provide data support for subsequent post-simulation and signal integrity analysis.

In practice, we ensure the chip's reliability and stability in terms of signal integrity through precise evaluation using parasitic parameter extraction tools.

5. PV Tools: Ensuring Design Compliance with Manufacturing Requirements

Physical verification tools are used to ensure that the design meets manufacturing requirements and has no logical or physical errors. Physical verification includes LVS and DRC. Commonly used physical verification tools include Hercules (Synopsys), Dracula (Cadence), and Calibre (Mentor). Among them, Calibre (Mentor) is the most widely used verification platform in the industry. It can perform comprehensive physical verification to ensure that the design will not have any problems during the manufacturing process.

1) Calibre is an "Edge-Based" tool, and the default error display is edge

2) Several commonly used Rules, please read Calibre's Handbook for details

• Internal (Inside to inside) is used to check Width and Overlap;

• External (Outside to the outside) is used to check Space and Notch;

• Enclosure (Inside and outside)

3) There are three types of control for the DRC check results: Euclidean (default), Square, and Opposite

In actual work, we use strict inspections of physical verification tools to ensure the integrity and manufacturability of the design at the physical level. Physical verification is an important part of the chip design process, used to ensure that the design layout meets manufacturing requirements. Physical verification mainly includes the following two key steps:

• DRC: Checks whether the design layout complies with the design rules provided by the Fab. The DRC tool detects line width, spacing, alignment and other issues in the layout to ensure that there will be no process problems in the manufacturing process.

• LVS: Compares the layout and schematic for consistency. The LVS tool checks whether the electrical connections in the layout are consistent with the schematic design to ensure that the electrical functions of the layout are correct.

Physical verification tools use the Design Rules (usually .drc & .lvs) provided by the Fab to perform checks. These tools will strictly perform verification according to the Fab design rules to ensure the manufacturability and functionality of the design.

The industrial chain status of EDA tools

1. Market value of EDA tools

According to data from the ESD Alliance, the global EDA market size will reach US$14.526 billion in 2023, a year-on-year increase of 1.8%. Most of the market space is occupied by the three overseas giants (Synopsys, Cadence, and Siemens EDA), with a combined share of nearly 80%, and a localization rate of less than 2%. This shows that EDA tools have extremely high market value and strategic significance in the integrated circuit industry.

2. Leverage Effect of EDA Tools

Although the market size of EDA tools is relatively small, its supporting role for the entire semiconductor industry is extremely significant. It is estimated that the scale of the semiconductor manufacturing industry directly supported by EDA tools exceeds 1 trillion US dollars.

3. EDA and IP profit model

DA manufacturers have two profit models: EDA companies' profits are mainly from software license authorization. Generally, domestic EDA companies charge according to the number of EDA tool licenses sold, and each license is usually sold for three years. The unit price of different EDA tools varies greatly. The complexity of digital back-end layout and routing tools is the highest, and the workload is also the largest in chip design, so the unit price of licenses is the most expensive. The second is analog design tools, and the third is digital front-end tools.

In addition to software license authorization, there is also a fee for design service fees, which is usually a supporting service of international EDA manufacturers. The chip design service is mainly to help companies without design experience, especially start-ups, such as companies that make AI chips. They are not good at making chips themselves, and they need to design chips that are very complex in advanced processes. Some international large manufacturers will provide special design services for such customers. The meaning of design services is to help these start-ups establish EDA processes on advanced processes, and take this opportunity to promote some of their own tools.

IP profit model:

Similar to EDA. It is mainly IP license authorization, and in most cases, it is charged based on the project. A project uses several IPs, each IP has a corresponding unit price, and then the sum is the IP licensing fee of the project. In addition, there is a similar design service concept. In addition to these two charging models, IP has an additional charging model, which is royalties. Chip design manufacturers use IP for mass production. After shipment, the IP supplier will take a proportion based on the shipment volume and unit price of the chip. There will be certain agreements at the beginning of the IP procurement contract, and the usual proportion is about a few tenths of a percent to 2%.

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