For decades, computing architectures have relied on dynamic random access memory (DRAM) as main memory, providing temporary storage space for processing units to retrieve data and program code. DRAM technology has been widely used in many electronic devices due to its high-speed operation, high integration, high cost-effectiveness and excellent reliability.

The DRAM bit cell (i.e., the element that stores one bit of information) has a very basic structure. It consists of a capacitor (1C) and a transistor (1T) integrated near the capacitor. The role of the capacitor is to store charge, while the transistor is used to access the capacitor in order to read the amount of stored charge or store new charge. The 1T-1C bit cells are arranged in an array containing word lines and bit lines, with the word lines connected to the gates of the transistors, which control access to the capacitors. The memory state can be read by sensing the charge stored on the capacitors through the bit lines.

Over the years, the memory community has introduced successive generations of DRAM technology through continuous bit cell density expansion. Current DRAM chips are of the "10nm class" (denoted as D1x, D1y, D1z, D1α…), where the half-pitch of the active area in the memory cell array ranges from 19nm to 10nm. The demand for better performance and higher capacity DRAM driven by artificial intelligence is driving research and development into the 10nm era. This requires innovations in capacitors, access transistors, and bit cell architecture. Examples of such innovations include high-aspect ratio pillar capacitors, the shift from saddle-shaped (FinFET-based) access transistors to vertical gate architectures, and the transition from 6F² to 4F² cell designs (F being the minimum feature size for a given technology node).

Planar 1T-1C DRAM chip internal details: peripheral circuits

In order to realize the full functionality of a DRAM chip, several other transistors are required in addition to the access transistors. These additional transistors perform functions such as address decoders, sense amplifiers, or output buffers. They are called DRAM peripheral transistors and are traditionally manufactured next to the DRAM memory array area.

Figure 1 – Inside a DRAM chip: the 1T-1C-based DRAM memory array and the DRAM peripheral area.

DRAM peripheral transistors fall into three broad categories. The first are conventional logic transistors: digital switches that turn on and off repeatedly. The second are sense amplifiers - analog-type transistors that sense the difference in charge between two bit cells. A small positive change is amplified to a high voltage (representing a logic 1), and a small negative change is amplified to zero voltage (representing a logic 0). These logic values are then stored in a latch structure called a row buffer. Sense amplifiers are typically located close to the memory array, taking up a large portion of the DRAM chip. The third category is row decoders: transistors that pass relatively high bias voltages (usually around 3V) to the memory elements to support write operations.

To keep pace with the node-to-node improvements in the memory array, DRAM peripherals have also evolved in terms of area reduction and performance improvements. In the long term, we may be able to envision more disruptive solutions that break away from the traditional "2D" DRAM chip architecture. One option is to manufacture the DRAM peripherals on a separate wafer and then bond it to the wafer containing the memory array, borrowing from the approach introduced in 3D NAND.

Single, cost-effective and thermally stable technology platform optimized for peripheral transistors

Each of the three groups of peripheral transistors has its own requirements. Conventional logic transistors must have good short channel control, high on-current (Ion), and low off-current (Ioff). Due to these characteristics, they are most similar to the logic transistors in a typical system-on-chip (SoC). They also need to allow for multiple threshold voltages (Vth) to meet different design requirements. The other two types of transistors have more different characteristics and do not exist in a typical logic SoC. Analog sense amplifiers require good amplification performance, which is due to the low threshold voltage (Vth).

In addition, because the signal is amplified, the mismatch between two adjacent sense amplifiers must be as low as possible. Therefore, the ideal sense amplifier is a repeatable transistor with good analog function. Finally, the row decoder is a digital transistor that requires a very thick gate oxide layer to withstand higher bias voltages compared to advanced logic nodes. This makes the transistor inherently more reliable, but at the expense of slower operation.

Figure 2: The main steps required to fabricate transistors for DRAM peripheral applications. Key blocks that require specific development are underlined.

In addition to these specific requirements, all peripheral transistors face a number of limitations. One of the key issues is thermal stability. In the current DRAM process flow, the DRAM memory array is located at the periphery and the peripheral transistors are manufactured before the DRAM memory elements. Therefore, the peripheral transistors undergo multiple thermal processes during the manufacturing process of the storage capacitors, access transistors, and memory back-end production lines. Therefore, the peripheral transistors must be able to withstand "DRAM memory annealing" temperatures of up to 550°C-600°C for up to several hours.

Second, the cost-effectiveness of DRAM chips must be maintained, driving integration choices towards simpler process solutions than those typically used in logic processes. To reduce costs, the memory industry also tends to adopt a single technology platform for various peripheral transistors, even though their requirements vary. In addition, the requirements for low leakage and low power consumption are more stringent, which benefits multiple DRAM use cases, especially mobile use cases.

The combination of all these specifications makes it impossible to directly copy the standard logic process flow. It requires optimization of specific modules, including the gate stack, source/drain junctions, and source/drain metal contacts of the transistor.

State-of-the-art DRAM peripherals

From SiON-based gate stacks to high-k/metal gates

Until 2018, DRAM peripheral transistors were mainly manufactured using planar logic MOSFET technology with either polysilicon/silicon dioxide (poly-Si/SiO²) or polysilicon/silicon oxide (poly-Si/SiON) gates. To maintain the cost per bit trend line for DRAM, these technologies were not as advanced as transistors used for high-performance logic. However, to keep pace with subsequent DRAM memory performance increases, peripheral technology had to improve. The most obvious candidate was to move to a planar transistor architecture with high-k/metal gate stacks - a shift that had already occurred in volume production of logic technology as early as 2007.

Since around 2007, imec and its partners have been actively exploring DRAM-compatible high-k/metal gate transistors and have proposed several materials and integration schemes to the memory industry. Today, almost all devices with built-in DRAM memory use planar peripheral transistor technology with high-k/metal gates, a technology that imec has been leading for more than 15 years. The following is an overview of some of the proposed materials, modules and integration schemes, which vary in manufacturing complexity and performance levels.

1. High-k/metal gate integration: thermally stable gate-first and gate-last integration flows

One of the solutions demonstrated by imec for possible early promotion is based on the "gate-first" integration approach, where the metal gate is deposited before the high-temperature source-drain junction activation anneal. The gate stacks for nMOS and pMOS can be optimized separately by using different work function metals and layer thicknesses (e.g., TiN/Mg/TiN for n-type and TiN for p-type).

One of the key parameters is to obtain an effective work function that is low enough for nMOS and high enough for pMOS to ensure a good I on / I off ratio. The researchers achieved this by doping the gate stack (different dopants for p and nMOS), which allows the threshold voltage to be changed. The choice of doping materials and their integration also provide a way to improve the thermal stability of the gate stack and achieve different V th required for DRAM chips. In addition, the specific requirements of DRAM for low gate leakage are met by using thicker gate stacks than logic-oriented solutions.

Figure 3 – Sketch of the key manufacturing steps in the gate-first integration approach for planar high-k/metal-gate periphery transistors

2. Optimizing the Source/Drain Junction

Source/drain junctions are critical to ensuring the functionality of MOSFET transistors. They are formed by creating a doping gradient in the source/drain region. As the length of the conductive channel continues to shorten, ultra-shallow junctions are essential to ensure good electrostatic control of the channel. However, for peripheral transistors, thermal treatment during annealing of DRAM memory can induce unwanted doping diffusion, requiring more complex process flows to maintain the doping gradient. This problem can be solved by changing the junction implant scheme, such as using pre-amorphization implants and junction co-implantation. Imec demonstrated several sets of optimized junctions for various threshold voltage targets.

3. Thermally Stable Silicide Process

A common challenge facing all transistors is to minimize the source/drain contact resistance. The source/drain contact is formed by contacting the metal to the source/drain region to form a Schottky barrier at the interface. To ensure low resistance, two techniques are usually used: (1) heavily doping the source/drain region; (2) fully silicide the source/drain region - silicide is formed by the reaction of the contact metal with the doped silicon. However, Ni(Pt) silicides traditionally used in logic devices cannot withstand the annealing temperatures associated with DRAM. Imec proposes a thermally stable NiPt-based silicide module with low contact resistance by implementing additional implantation and annealing steps to stabilize the silicide.

Next Generation

Thermally Stable FinFET-Based Peripheral Platform for Improved Power, Performance, and Area

Increasingly stringent requirements for DRAM memory for applications such as automotive, artificial intelligence and machine learning are driving the need for faster, more reliable and more energy-efficient peripheral transistors. One option is to retrace the path of “logic” and move from planar high-k/metal gate transistors to FinFETs. The logic roadmap made this shift as early as 2011 after R&D work clearly demonstrated the superior performance of fin-shaped conductive channel transistors: improved I on /I off, better short channel control, higher drive current in a reduced footprint (due to a larger effective channel width) and lower power consumption – all while keeping costs in check. Most importantly, the use of high-level fins reduces threshold voltage mismatch, which is particularly beneficial for DRAM sense amplifiers.

As with the planar version, the specific requirements of DRAM do not allow for a straight-forward copy of the FinFET process flow developed for conventional logic. To this end, imec has developed a thermally stable peripheral technology platform based on FinFETs and integrated modules optimized for DRAM. The industry has proposed several options with different performance-cost trade-offs for its next-generation DRAM products.

1. Thermally stable gate-first and gate-last FinFET integration processes

In 2021, imec reported the first experimental demonstration of a thermally robust integration process for FinFETs that uses an optimized gate-first approach to achieve high-k/metal gate stacks. Compared to the traditional gate-first approach, the improved process achieves gate stacks with the same thickness and the same work function metal for n-type and pMOS. The so-called Vth shifter material is then diffused into the high-k dielectric to adjust the effective work function of the n-type and pMOS devices. This improved gate-first approach reduces gate asymmetry and improves the thermal stability of the process. By using this process, the researchers demonstrated improved I on /I off and short channel control relative to planar high-k/metal gate counterparts. These indicators did not drop after DRAM-specific annealing. Processes with taller fins (up to 80 nm) have also been developed with improved threshold voltage mismatch and area gain.

Figure 4 – Example of high-k/metal gate fin fabrication. TEM cross-sections of 40nm, 65nm, and ~80nm high fins are shown.

One disadvantage of the gate-first integration approach is the relatively high threshold voltage, which stems from the effect of high-temperature annealing on the gate stack during junction activation. This problem can be solved by the gate-last (or RMG) integration approach, but this approach requires additional process steps. At IEDM 2022, imec demonstrated a thermally stable FinFET gate-last process flow.

Figure 5 – Proposed gate-last process flow selection for thermally stable FinFETs

Optimized thermally stable gate

Last FinFET process using Mo-based work function metal for pMOS

A typical feature of a gate-last process is the use of different work function metals for nMOS and pMOS devices. At the 2024 VLSI Conference, imec demonstrated the performance benefits of using a novel Mo-based work function metal in pMOS instead of the traditional TiN-based approach. The new gate stack module has been successfully integrated into a gate-last FinFET process and proven to be thermally stable. The DRAM-compatible process with integrated Mo-based p work function metal provides sufficiently low Ioff current and low threshold voltage (0.12V) for pMOS devices. The FinFET was also benchmarked against a thermally stable planar high-k/metal gate as reference, showing up to three times higher Ion (at target Ioff) for the same Si footprint. These results make the thermally stable gate-last FinFET process a valuable candidate for DRAM periphery logic below 10nm.

Figure 6 – (Left and center) STEM images of the fins on the ring oscillator and (right) elemental mapping (EDS) on the gate, showing CMOS patterning and good conformality of the Mo-based p-work function metal stack

Thermally stable niobium-based metal contacts with low contact resistance

In early work on peripheral transistors based on planar high-k/metal gates, imec researchers reduced source-drain contact resistance by improving doping profiles and adding pre-amorphization implants. At IEDM 2024, imec introduced a different approach: replacing the traditional Ti contact metal for pMOS devices with Nb. The thermal stability of Nb-based contact modules was demonstrated for the first time. In addition, when integrated into the gate-last FinFET platform, superior performance was observed: record low contact resistance, lower total parasitic resistance, and higher Ion.

Figure 7 – Comparison of contact resistivity of Ti-based and Nb-based contact modules (different thicknesses) before and after DRAM annealing

In the long term, we envision that more disruptive concepts will emerge to continue the path of DRAM scaling. One of these is to build the peripheral circuits on a separate wafer and integrate them with the memory array using advanced wafer bonding technology. Although this approach requires additional process steps, the real benefit is reduced requirements for thermal stability because the peripheral circuits are now manufactured separately from the memory array.

Reference link https://www.imec-int.com/en/articles/technology-platform-thermally-stable-dram-peripheral-transistors

Source: Semiconductor Industry Observer

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