Only three companies in the world can mass-produce state-of-the-art computer chips with incredible precision. Last month, a Japanese startup took the first step toward becoming the fourth. On April 1, Rapidus reached a key milestone when it launched and tested its pilot line of 2-nanometer node chips using a recipe developed in collaboration with IBM (based on the latter's nanosheet transistor structure). Rapidus told IEEE Spectrum that more than 200 cutting-edge instruments installed at its new fab in Chitose are now ready for operation, including the key piece of equipment: a state-of-the-art extreme ultraviolet (EUV) lithography system valued at more than $300 million.

"We broke ground in September 2023," said Henri Richard, president of Rapidus Design Solutions, which was founded in Santa Clara, Silicon Valley, last April and is responsible for U.S. business development. "Surprisingly, at the beginning of the second quarter of 2025, we completed the first exposure of the EUV lithography system and are now ready to start trial production." 

About Rapidus

Regarding when Rapidus will launch the first test chips, Rapidus CEO Atsuyoshi Koike told The Japan Times in an interview in April: "Prototype chips may be produced in July." In a company statement, the company clarified media reports about negotiations with customers and said it was in talks with "many potential customers, from large established companies to AI startups."

Rapidus was founded in August 2020 with backing from a consortium of eight domestic Japanese companies: Denso, Kioxia, MUFJ Bank, NEC, NTT, Softbank, Sony, and Toyota. But central government support has proven more important as part of efforts to revitalize the country's advanced semiconductor industry. Japan's support is based on concerns about national security, given the country's reliance on potentially vulnerable overseas suppliers for cutting-edge chips. (The U.S. has also moved to reduce its reliance on Japan for the same reason.) Government subsidies have totaled 1.72 trillion yen ($12 billion) to date. Yet the eight founders' equity investment remains just 7.3 billion yen ($51 million), raising concerns about Rapidus' future. The new foundry estimates that it will need about 5 trillion yen ($35 billion) to achieve its mass production goals.

Yet Rapidus's situation is not unlike that of Taiwan Semiconductor Manufacturing Co. (TSMC), now the industry's largest chipmaker, when it was founded in the 1990s. Atsushi Osanai, a professor at Waseda University's Graduate School of Business and Finance, noted that at the time, as in Japan, the Taiwanese government supported the startup, while private companies "were not initially enthusiastic." "Similarly, Japanese private companies took a wait-and-see approach to Rapidus. The key factor was whether the government would provide enough support for Rapidus to incentivize the private sector."

Rapidus Development

Rapidus is off to a fast start, but its 2027 2nm shipping date could be two years behind the industry's three leading-edge silicon wafer producers, TSMC, Intel, and Samsung, which are reportedly likely to start mass production of 2nm chips in the second half of this year.

To catch up and compete, Rapidus is taking a different tack from the mass wafer production model favored by the three major manufacturers. In TSMC's case, their business model focuses on processing large batches of wafers for the production of large quantities of devices such as GPUs and CPUs, and maintaining high yields, while relying on rigid processing methods that can only be improved incrementally. In contrast, Rapidus will use a single-wafer process to produce specialized chips for specific applications, custom chips for niche markets, and later large-volume orders.

As the name implies, the single-wafer approach processes each wafer individually, rather than in batches. Although many wafers can pass through the production line at the same time, each wafer is processed individually at each stage of the process. Rapidus will also apply a newly developed scheme called design-manufacturing co-optimization (DMCO). The company claims this will facilitate design by connecting it to manufacturing, which can also help offset the throughput drop caused by eliminating batch processing. By using AI to optimize production parameters, DMCO aims to increase design speed and yield. This requires extensive use of sensors inside the equipment to measure parameters such as temperature, gas density, and reaction rates to collect large amounts of production data for AI analysis.

"This will allow us to measure the processing of individual wafers, learn from the results, and quickly feed data back into the system," Richard explained. "To increase yield, parameters must be constantly adjusted, and these changes depend on the data acquired during processing."

In addition, he added that the fab is using a "revolutionary grid transport system that allows us to move wafers to any position during processing, thus avoiding the traffic jams that occur when machines fail or have problems in standard fabs with linear transport systems."

"Taking a lot of data from the manufacturing process and feeding it back into the system to improve yield faster will reduce time to market for Rapidus customers," said Tadahiro Kuroda, a professor of engineering at the University of Tokyo who worked at Toshiba Corp.'s semiconductor division for 18 years before moving to academia. "This is an ideal solution for semiconductor manufacturing and makes a lot of sense."

Rapidus Issues

However, because Rapidus relies on a host of new technologies, it could run into teething problems that could extend its time to mass-deliver products. Meanwhile, competitors are scrambling to catch up. In April, TSMC unveiled its next-generation A14 process, equivalent to a 1.4-nanometer node chip, which it plans to "enter production in 2028."

"Technically, Rapidus' success depends on the smooth progress of semiconductor prototype development for mass production in 2027," Osanai said. "With only two years to achieve mass production, this is critical to the company's success."

Other experts are more optimistic. Kuroda said that given the huge growth expected in AI applications and emerging AI data centers, and the resulting surge in power consumption, "demand for 2-nanometer chips will be huge," as these semiconductors are expected to reduce power consumption by more than 30% compared to today's cutting-edge silicon wafers. "As a result, demand for AI-related semiconductors is expected to exceed the capacity of existing foundries."

If the latter view holds true and Rapidus can achieve its mass production goals on time, then this government-backed effort to make Japan a powerhouse in advanced chip manufacturing again may become a winning bet rather than a reckless gamble.

Source: This article is compiled from IEEE

Reference link https://spectrum.ieee.org/rapidus-japan-semiconductor

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