JEDEC Solid State Technology Association, the global leader in developing standards for the microelectronics industry, today announced the release of the much-anticipated High Bandwidth Memory (HBM) DRAM standard: HBM4.

About HBM4

JESD270-4 HBM4 is designed as an evolutionary step beyond the previous HBM3 standard, further increasing data processing rates while maintaining the fundamental characteristics of higher bandwidth, power efficiency, and greater capacity per chip and/or stack, as higher bandwidth enables higher data processing rates.

The improvements brought by HBM4 are critical for applications that require efficient processing of large data sets and complex calculations, including generative artificial intelligence (AI), high-performance computing (HPC), high-end graphics cards, and servers. HBM4 offers several improvements over previous versions of the standard, including:

Increased bandwidth: With a 2048-bit interface and transfer speeds of up to 8 Gb/s, HBM4 increases total bandwidth to 2 TB/s.

Double the number of channels: HBM4 doubles the number of independent channels per stack from 16 channels (HBM3) to 32 channels, each with 2 pseudo channels. This provides designers with greater flexibility and independent ways to access the cube.

Power Efficiency

JESD270-4 supports vendor-specific VDDQ (0.7V, 0.75V, 0.8V, or 0.9V) and VDDC (1.0V or 1.05V) levels, resulting in lower power consumption and improved energy efficiency.

Compatibility and Flexibility

The HBM4 interface definition ensures backward compatibility with existing HBM3 controllers, allowing for seamless integration and flexibility in a variety of applications, and allowing a single controller to work with both HBM3 and HBM4 when needed.

Directed Refresh Management (DRFM)

HBM4 incorporates Directed Refresh Management (DRFM) to improve row-hammer mitigation capabilities and reliability, availability, and serviceability (RAS).

Capacity

HBM4 supports 4-high, 8-high, 12-high, and 16-high DRAM stack configurations with 24Gb or 32Gb die density, providing higher cube density of 64GB (32Gb 16-high).

"High-performance computing platforms are rapidly evolving, requiring innovation in memory bandwidth and capacity," said Barry Wagner, technical marketing director at NVIDIA and chair of the JEDEC HBM Subcommittee. "HBM4 was developed by NVIDIA in collaboration with technology industry leaders to enable a quantum leap in efficient, high-performance computing for AI and other accelerated applications."

"JEDEC members are committed to developing the standards needed to support future technologies," said Mian Quddus, chairman of the JEDEC Board of Directors. "The HBM Subcommittee's continued efforts to improve the HBM standard are expected to drive significant advances across a wide range of application areas," he added.

"The dramatic growth in AI model size requires higher memory bandwidth to improve the efficiency of AI hardware systems with heterogeneous compute architectures, ensuring large amounts of data can move quickly and seamlessly," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "The HBM4 standard addresses this higher bandwidth need with significant enhancements. Working with JEDEC and ecosystem partners, Cadence is advancing the industry's HBM4 by delivering the highest performance, most power-efficient, and most area-efficient HBM4." 

"Memory bandwidth is one of the key pillars of performance for AI computing systems. JEDEC HBM4 represents a big step forward for Google in terms of the bandwidth required for next-generation training and inference systems," said Nikhil Jayaram, vice president of Google Cloud Chip. "We expect HBM4-based systems to drive AI advancements and look forward to working with JEDEC on the future of HBM."

Reference link https://www.hpcwire.com/off-the-wire/jedec-releases-hbm4-standard-to-advance-ai-and-hpc-memory/

Source: Content compiled from hpcwire

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