At recent meetings, there has been much discussion about TSMC customers sending wafers to Intel for packaging. The question is, why? Is it due to price competitiveness? Capacity? Or supply chain diversification? During the last investor call, this question was raised, and CC Wei's answer was impeccable:

Jeff Su: To put it simply, in his view, EMIB-T is gaining momentum. How should we view the competitive threat this poses?

CC Wei: Well, I would say that our current packaging capacity is very tight, which has limited our customers' growth. We welcome this additional flexibility in the market. This will help the growth of TSMC's front-end wafer business, which is a major component of TSMC's business. According to reports, this technology looks promising. We hope they will succeed and share some of TSMC's capacity. Currently, we are working to close the supply-demand gap. As I said, we welcome this additional option, which provides greater flexibility for my customers.

What are the differences between TSMC CoWoS and Intel EMIB?

TSMC's CoWoS and Intel's EMIB are advanced packaging platforms designed to overcome the economic and physical size limitations of monolithic system-on-a-chip (SoC). Both support heterogeneous integration of logic, memory, and application-specific chips within a single package, but they employ drastically different interconnect architectures. CoWoS typically creates a wide, high-density interconnect plane beneath the chip, while EMIB only places small silicon bridges when high-density communication is required between adjacent chips. This architectural difference leads to variations in bandwidth allocation, package size, cost, thermal performance, and design methodologies.

About CoWoS

CoWoS (Chip-Wafer-Substrate) is part of TSMC's 3DFabric portfolio and is widely used in high-performance computing and artificial intelligence processors. In CoWoS-S, logic chips and high-bandwidth memory stacks are mounted on a passive silicon interposer containing fine-pitch wiring and through-silicon vias (TSVs). This interposer is then connected to an organic packaging substrate. Because high-density wiring can be performed over almost the entire area beneath the active chips, CoWoS-S supports extremely wide parallel interfaces, predictable signal paths, and robust chip-to-chip interconnect capabilities. TSMC states that CoWoS-S supports interposers up to approximately 3.3 photomasks (or 2700 square millimeters), while CoWoS-L and CoWoS-R support even larger systems.

The CoWoS process family offers broader application than single silicon interposer processes. CoWoS-R uses a multilayer redistribution layer (RDL) interposer instead of a large silicon interposer, reducing reliance on bulk interposer silicon. CoWoS-L combines an RDL-based interposer with local silicon interconnects for areas requiring higher wiring density. These variants allow designers to weigh maximum wiring density against package size, cost, and manufacturing complexity. Therefore, comparing EMIB solely to CoWoS-S underestimates TSMC's architectural flexibility. CoWoS-L, in particular, employs a localized silicon structure, somewhat resembling a bridge package. Both CoWoS-R and CoWoS-L are slated for mass production by 2024 or later.

Differences between Intel and CoWoS

Intel's Embedded Multi-Chip Interconnect Bridge (EMIB) embeds small, passive silicon bridges within an organic package substrate. Microbumps connect the edges of adjacent chips to fine-pitch wiring on each bridge, while traditional substrate traces transmit low-density signals elsewhere. Therefore, EMIB avoids the silicon interposer and its associated through-silicon vias (TSVs) across the package. Intel positions EMIB as an integration of logic-to-logic and logic-to-HBM, and reports mass production deployments since 2017. Newer options include EMIB-M (integrating metal-insulator-metal capacitors) and EMIB-T (adding TSVs to the bridges for enhanced vertical connectivity and power delivery).

From an electrical perspective, CoWoS-S provides the most uniform high-density wiring environment. Large interposers can distribute thousands of short connections across a central accelerator, multiple HBM stacks, and additional chipsets without confining dense links to the chip edges facing the bridge. This feature is particularly important when extensive connectivity is required across a large portion of the package. The continuous interposer also allows designers to integrate power distribution structures and decoupling capacitors close to active devices.

EMIB offers higher silicon utilization when communication is limited to adjacent chips. It provides short, dense interconnects without the need for interposers beneath components that don't require fine-pitch wiring, saving silicon area. However, complex topologies may require multiple bridges, meticulous chip layout planning, and additional organic substrate traces between non-adjacent components. The package architecture must precisely align the bridge locations with the edges and interfaces of each chip.

The mechanical and manufacturing tradeoffs are equally subtle. Eliminating the large silicon interposer reduces material usage and some wafer fabrication steps, giving EMIB potential cost and yield advantages with proper design. Fabricating its organic substrate remains challenging because the bridge structure must be precisely embedded, planarized, and aligned. CoWoS-S adds a large, thin silicon structure, increasing process complexity in its fabrication, handling, warpage control, and assembly of known-good chips. Nevertheless, its conventional interposer provides a mature and predictable wiring platform. CoWoS-R and CoWoS-L attempt to mitigate the size, cost, and manufacturability limitations of all-silicon interposers.

Neither architecture automatically addresses thermal issues. They both tightly pack high-power logic chips and HBM stacked chips, exacerbating thermal coupling and localized heat density. The CoWoS architecture can accommodate large logic memory arrays, but as intermediate layers and package sizes increase, issues such as package warpage, power supply, and heat dissipation become more challenging. The EMIB architecture allows for relatively flexible chip placement and avoids continuous silicon layers, but its thermal performance still largely depends on chip power, spacing, heatsink design, package materials, and system-level thermal management.

Both technologies support vertical integration. Intel combines EMIB with Foveros chip stacking technology to produce EMIB 3.5D systems containing multiple horizontally and vertically integrated chipsets. TSMC combines CoWoS with its SoIC wafer-level stacking platform. These combinations allow designers to vertically place cache, logic, or dedicated functions while leveraging CoWoS or EMIB for package-level horizontal interconnects.

Therefore, the actual selection criterion is interconnect architecture, not simply performance ranking. The CoWoS-S approach is most effective when the system requires a large-area, continuous, and extremely high-density interconnect architecture, especially between accelerators and multiple HBM stacks. The CoWoS-R and CoWoS-L approaches extend this approach to larger sizes or more cost-conscious products. The EMIB approach is most effective when high-bandwidth links are concentrated at specific chip boundaries, and designers prioritize silicon efficiency, modularity, and avoiding the use of full interposers.

In summary: CoWoS emphasizes an interposer-centric system architecture, while EMIB emphasizes localized silicon bridges embedded in organic substrates. The better choice depends on interface width, communication topology, package size, power supply capabilities, thermal constraints, assembly yield, design tool support, manufacturing process, and total system cost, not just package density.

Source: Compiled from semiwiki

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